K. Suguro

发表

FinFET: the prospective multi-gate device for future SoC applications

H. Ishiuchi, N. Aoki, S. Inaba, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

Katsuya Okumura, Tsuyoshi Shibata, K. Suguro, 2002 .

New Guidelines of Optimizing SALICIDE Structure for High Speed CMOS LSI

Kazuya Ohuchi, Hisao Yoshimura, K. Suguro, 1999 .

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions

H. Koike, Y. Akasaka, K. Nakajima, 1996, International Electron Devices Meeting. Technical Digest.

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

Hiroshi Iwai, Tatsuya Ohguro, Yasuhiro Katsumata, 1995 .

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

K. Nakajima, K. Sekine, K. Suguro, 2005, IEEE Transactions on Electron Devices.

High aspect ratio hole filling by tungsten chemical vapor deposition combined with a silicon sidewall and barrier metal for multilevel interconnection

H. Tango, Yasushi Nakasaki, K. Suguro, 1987 .

High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

Y. Akasaka, K. Nakajima, K. Suguro, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A self-aligned emitter base NiSi electrode technology for advanced high-speed bipolar LSIs

Y. Katsumata, H. Iwai, H. Nakajima, 1992, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Y. Akasaka, Y. Toyoshima, K. Nakajima, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via-Plugs

Hideaki Hirabayashi, Tadashi Iijima, Toshio Shimizu, 1995 .

A NiSi salicide technology for advanced logic devices

Y. Katsumata, H. Iwai, H. Nakajima, 1991, International Electron Devices Meeting 1991 [Technical Digest].

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

Yoshitaka Tsunashima, Katsuhiko Hieda, Y. Akasaka, 2000 .

Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing

K. Suguro, K. Suguro, K. Nishinohara, 2004, IEEE Transactions on Semiconductor Manufacturing.

Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics

K. Nakajima, K. Suguro, K. Matsuo, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Issues and optimization of millisecond anneal process for 45 nm node and beyond

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

Y. Akasaka, K. Nakajima, M. Kinugawa, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Overview of the prospects of ultra-rapid thermal process for advanced CMOSFETs

K. Suguro, K. Matsuo, K.T. Nishinohara, 2004, The Fourth International Workshop on Junction Technology, 2004. IWJT '04..

Manufacturable local interconnect technology fully compatible with titanium salicide process

Y. Toyoshima, I. Kunishima, K. Suguro, 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.

A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIs

T. Ohguro, H. Iwai, I. Kunishima, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Improvement of threshold voltage deviation in damascene metal gate transistors

Yoshitaka Tsunashima, Tsuyoshi Shibata, Atsushi Yagishita, 2001 .