C. V. Niras

VLSI architecture of multiplier-less DWT image processor

Yinan Kong, Azadeh Safari, C. V. Niras, 2013, IEEE 2013 Tencon - Spring.

Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution

Vinu Thomas, C. V. Niras, 2012, 2012 International Symposium on Electronic System Design (ISED).

LMS algorithm implementation in FPGA for noise reduction and echo cancellation

Yinan Kong, C. V. Niras, 2012 .

Overlapped block-processing VLSI architecture for separable 2D filters

Azadeh Safari, C. V. Niras, Yinan Kong, 2015 .

Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling

Yinan Kong, Azadeh Safari, C. V. Niras, 2016, Integr..

A novel angle-restricted test zone search algorithm for performance improvement of HEVC

Manoranjan Paul, Yinan Kong, C. V. Niras, 2017, 2017 IEEE International Conference on Image Processing (ICIP).

An Efficient ASIC Design of Variable-Length Discrete Cosine Transform for HEVC

Yinan Kong, C. V. Niras, Cheeckottu Vayalil Niras, 2016, 2016 European Modelling Symposium (EMS).

High-performance elliptic curve cryptography processor over NIST prime fields

Yinan Kong, Md. Selim Hossain, C. V. Niras, 2017, IET Comput. Digit. Tech..