Young-Shying Chen

A Complete Asymmetric Drain Current Model For Post-stress Submicron pMOSFET's

Sheng-Lyang Jang, Young-Shying Chen, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

Characteristics improvement of 4H-SiC using termination with P-Well enclosure in P-Plus floating guard rings for 1700V DMOSFETs

Jeng-Hua Wei, Young-Shying Chen, Cheng-Tyng Yen, 2014, 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD).

Write Disturbance Modeling and Testing for MRAM

Cheng-Wen Wu, Chin-Lung Su, Ming-Jer Kao, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Testing MRAM forWriteDisturbance Fault

Chin-Lung Su, Young-Shying Chen, Chien-Chung Hung, 2006 .

Degradation of bipolar junction transistors under dynamic high current stress and biased in open-collector condition

Sheng-Lyang Jang, Young-Shying Chen, Ping-Chen Chang, 1994 .

Testing MRAM for Write Disturbance Fault

Cheng-Wen Wu, Chin-Lung Su, Ming-Jer Kao, 2006, 2006 IEEE International Test Conference.

Modeling and design of the high performance step SOI-LIGBT power devices by partition mid-point method

Young-Shying Chen, Huang-Chung Cheng, Chorng-Wei Liaw, 2003 .