Kyung-Ryun Kim

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

Nam Sung Kim, Chang-Kyo Lee, Hyung-Joon Chi, 2021, IEEE Journal of Solid-State Circuits.

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

Byung-Gil Jeon, Wook-Ghee Hahn, Ki-Whan Song, 2012, 2012 IEEE International Solid-State Circuits Conference.