S. Subramanian

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).