Shujiang Ji

A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS

N. Yan, Bowen Chen, Yizhuo Wang, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL

Hao Min, Jun Tao, Jiahe Shi, 2023, IEEE Journal of Solid-State Circuits.

A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM

Hao Min, N. Yan, Xinyi Lin, 2022, IEEE Microwave and Wireless Components Letters.