N. Togawa

A processor core synthesis system in IP-based SoC design

M. Yanagisawa, T. Ohtsuki, N. Tomono, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Test data volume for multiscan-based designs through single/sequence mixed encoding

M. Yanagisawa, T. Ohtsuki, N. Togawa, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Experimental evaluations of high-level energy optimization based on thread partitioning

M. Yanagisawa, T. Ohtsuki, J. Uchida, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Reconfigurable adaptive FEC system with interleaving

T. Ikenaga, S. Goto, K. Shimizu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A reconfigurable adaptive FEC system for reliable wireless communications

T. Ikenaga, M. Yanagisawa, T. Ohtsuki, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

High-level synthesis algorithms with floorplaning for distributed/shared-register architectures

M. Yanagisawa, T. Ohtsuki, N. Togawa, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An efficient algorithm/architecture codesign for image encoders

T. Ikenaga, M. Yanagisawa, T. Ohtsuki, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Area/delay estimation for digital signal processor cores

M. Yanagisawa, T. Ohtsuki, Y. Miyaoka, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).