Hyang-Ja Yang

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming

Won-Tae Kim, Daehan Kim, Dae-Seok Byeon, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip

Sunghoon Kim, Jin-Tae Kim, Min-Jae Lee, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

Wook-Ghee Hahn, Hyun Wook Park, Jeong-Don Ihm, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Jae-Hyung Lee, Young-Hyun Jun, Dae-Hyun Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Young-Hyun Jun, Dong-Min Kim, Young-Sik Kim, 2010, 2010 Symposium on VLSI Circuits.

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

Wook-Ghee Hahn, Hyun Wook Park, Jeong-Don Ihm, 2016, IEEE Journal of Solid-State Circuits.

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

Jeong-Don Ihm, Dae-Seok Byeon, Jinho Ryu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

Jonghoon Park, Hyun Wook Park, Min-Seok Kim, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2011, IEEE Journal of Solid-State Circuits.