Noriyuki Miura

发表

15.8 A permanent digital archive system based on 4F2 x-point multi-layer metal nano-dot structure

Makoto Nagata, Noriyuki Miura, Shijia Liu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage

Jean-Luc Danger, Yu-ichi Hayashi, Julien Bringer, 2014, IEICE Trans. Electron..

Protecting cryptographic integrated circuits with side-channel information

Yu-ichi Hayashi, Makoto Nagata, Daisuke Fujimoto, 2017, IEICE Electron. Express.

On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis

Jean-Luc Danger, Makoto Nagata, Julien Bringer, 2013, 2013 International Symposium on Electromagnetic Compatibility.

47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Tadahiro Kuroda, Noriyuki Miura, Mitsuko Saito, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation

Makoto Nagata, Noriyuki Miura, Yoshihide Komatsu, 2020, IEICE Trans. Electron..

A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor

Yu-ichi Hayashi, Makoto Nagata, Takafumi Aoki, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Active Gain Scheduling (A Collaboration between LPV Plants and Gain Scheduling Controllers)

Kazuhiko Hiramoto, Noriyuki Miura, Mitsutaka Kawamura, 2008 .

Let's go to IEICE Workshops!: Hardware Security (HWS)@@@安心安全社会の根幹を支えるためのハードウェアセキュリティ時限研究専門委員会（HWS）

Noriyuki Miura, Noriyuki Miura, 2017 .

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2012, 2012 International Conference on Field-Programmable Technology.

A 0.025–0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2012, IEEE Journal of Solid-State Circuits.

Side-channel leakage from sensor-based countermeasures against fault injection attack

Takeshi Sugawara, Makoto Nagata, Noriyuki Miura, 2019, Microelectron. J..

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Jean-Luc Danger, Makoto Nagata, Noriyuki Miura, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor

Takeshi Sugawara, Tatsuya Fujii, Makoto Nagata, 2018, IEEE Journal of Solid-State Circuits.

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2012, IEEE Journal of Solid-State Circuits.

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan

Makoto Nagata, Takuji Miki, Daisuke Fujimoto, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

HT-detection method based on impedance measurements of ICs

Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura, 2018 .

Authentication Using Side-Channel Information

Makoto Nagata, Takaaki Mizuki, Noriyuki Miura, 2015, IACR Cryptol. ePrint Arch..

A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking

Tadahiro Kuroda, Noriyuki Miura, Yasuhiro Take, 2011, 2011 IEEE International Solid-State Circuits Conference.

A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines

Shinya Nakano, Tadahiro Kuroda, Hiroki Ishikuro, 2013, IEEE Journal of Solid-State Circuits.

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2017, IEICE Trans. Electron..

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping

Tadahiro Kuroda, Hiroki Ishikuro, Takayasu Sakurai, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

632 Active gain scheduling : A Collaboration between LPV Plants and Gain Scheduling Controllers

Kazuhiko Hiramoto, Noriyuki Miura, Mitsutaka Kawamura, 2007 .

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE

Makoto Nagata, Jean-Luc Danger, Noriyuki Miura, 2021, IEEE Transactions on Information Forensics and Security.

Programmable Bus for NAND Flash Memory Stacking

Tadahiro Kuroda, Hiroki Ishikuro, Takayasu Sakurai, 2009 .

On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils

Makoto Nagata, Noriyuki Miura, Taisuke Hayashi, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

3D clock distribution using vertically/horizontally-coupled resonators

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique

Tadahiro Kuroda, Hiroki Ishikuro, Kiichi Niitsu, 2007 .

A 12Gb/s non-contact interface with coupled transmission lines

Shinya Nakano, Tadahiro Kuroda, Hiroki Ishikuro, 2011, 2011 IEEE International Solid-State Circuits Conference.

A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs

Tsutomu Matsumoto, Makoto Nagata, Daisuke Fujimoto, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Tadahiro Kuroda, Takayasu Sakurai, Noriyuki Miura, 2009, IEEE J. Solid State Circuits.

An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM

Tadahiro Kuroda, Noriyuki Miura, Mitsuko Saito, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

IC-level hardware security and safety for smart society

Noriyuki Miura, 2017, 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

An FPGA-compatible PLL-based sensor against fault injection attack

Makoto Nagata, Wei He, Shivam Bhasin, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Cross talk countermeasures in inductive inter-chip wireless superconnect

Tadahiro Kuroda, Takayasu Sakurai, Noriyuki Miura, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Enhancing reactive countermeasure against EM attacks with low overhead

Makoto Nagata, Takafumi Aoki, Daisuke Fujimoto, 2017, 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI).

Rotary coding for power reduction and S/N improvement in inductive-coupling data communication

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2011, IEEE Asian Solid-State Circuits Conference 2011.

An 11Gb/s Inductive-Coupling Link with Burst Transmission

Tadahiro Kuroda, Hiroki Ishikuro, Takayasu Sakurai, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Side-channel leakage on silicon substrate of CMOS cryptographic chip

Jean-Luc Danger, Yu-ichi Hayashi, Makoto Nagata, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Constant Magnetic Field Scaling in Inductive-Coupling Data Link

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2008, IEICE Trans. Electron..

6W/25mm2 inductive power transfer for non-contact wafer-level testing

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack

Takeshi Sugawara, Tatsuya Fujii, Yu-ichi Hayashi, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Simultaneous 6Gb/s data and 10mW power transmission using nested clover coils for non-contact memory card

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2010, 2010 Symposium on VLSI Circuits.

EM attack sensor: Concept, circuit, and design-automation methodology

Yu-ichi Hayashi, Makoto Nagata, Takafumi Aoki, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

Tadahiro Kuroda, Noriyuki Miura, Shusuke Kawai, 2010, 2010 Symposium on VLSI Circuits.

Wideband Inductive-coupling Interface for High-performance Portable System

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2007, 2007 IEEE Custom Integrated Circuits Conference.

An extended XY coil for noise reduction in inductive-coupling link

Tadahiro Kuroda, Noriyuki Miura, Mitsuko Saito, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor

Jean-Luc Danger, Makoto Nagata, Noriyuki Miura, 2017, 2017 Symposium on VLSI Circuits.

6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2012, IEICE Trans. Electron..

Reflection compensation scheme for the efficient and accurate computation of waveguide discontinuities in photonic crystals

K. J. Vinoy, Irma Shamatava, Keith D. Paulsen, 2004 .

In-stack monitoring of signal and power nodes in three dimensional integrated circuits

Makoto Nagata, Noriyuki Miura, Yuuki Araga, 2014, 2014 International Symposium on Electromagnetic Compatibility, Tokyo.

A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor

Yu-ichi Hayashi, Makoto Nagata, Takafumi Aoki, 2015, The 20th Asia and South Pacific Design Automation Conference.

Attack sensing against EM leakage and injection

Shivam Bhasin, Noriyuki Miura, 2016, 2016 International SoC Design Conference (ISOCC).

PLL to the rescue: A novel EM fault countermeasure

Jean-Luc Danger, Makoto Nagata, Wei He, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices

Makoto Nagata, Takuji Miki, Naoya Watanabe, 2020, IEEE Journal of Solid-State Circuits.

Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF

Masanori Takahashi, Makoto Nagata, Noriyuki Miura, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

TCAD Driven Drain Engineering for Hot Carrier Reduction of 3.3 V I/O PMOSFET( the IEEE International Conference on SISPAD '02)

Noriyuki Miura, Marie Mochizuki, Koichi Fukuda, 2003 .

A Wafer test method of inductive-coupling link

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

An IC-level countermeasure against laser fault injection attack by information leakage sensing based on laser-induced opto-electric bulk current density

Yuichi Komano, Makoto Nagata, Noriyuki Miura, 2020, Japanese Journal of Applied Physics.

Integrated-circuit countermeasures against information leakage through EM radiation

Yu-ichi Hayashi, Makoto Nagata, Takafumi Aoki, 2014, 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC).

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs

Makoto Nagata, Takuji Miki, Naoya Watanabe, 2019, 2019 International 3D Systems Integration Conference (3DIC).

On-chip and on-board RF noise coupling and impacts on LTE wireless communication performance (Invited)

Makoto Nagata, Satoshi Tanaka, Masahiro Yamaguchi, 2015, 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link

Tadahiro Kuroda, Takayasu Sakurai, Kiichi Niitsu, 2007, IEICE Trans. Electron..

A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration

Tadahiro Kuroda, Hiroki Ishikuro, Kiichi Niitsu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor

Yu-ichi Hayashi, Makoto Nagata, Takafumi Aoki, 2014, CHES.

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

Shinya Nakano, Tadahiro Kuroda, Hiroki Ishikuro, 2012, 2012 IEEE International Solid-State Circuits Conference.

EMI performance of power delivery networks in 3D TSV integration

Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda, 2016, 2016 International Symposium on Electromagnetic Compatibility - EMC EUROPE.

Non-contact High-Speed Data Links for Memory Interfaces(Invited Talk)

Shinya Nakano, Tadahiro Kuroda, Hiroki Ishikuro, 2012 .

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

Tadahiro Kuroda, Hideharu Amano, Kiichi Niitsu, 2009, 2009 International Conference on Field Programmable Logic and Applications.

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013 .

Immunity evaluation of inverter chains against RF power on power delivery network

Makoto Nagata, Noriyuki Miura, Yuji Harada, 2013, 2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo).

Systematic Yield Simulation Methodology Applied to Fully-Depleted SOI MOSFET Process

Noriyuki Miura, Kenji Nishi, Hirokazu Hayashi, 2000 .

Supply-Chain Security Enhancement by Chaotic Wireless Chip-Package-Board Interactive PUF

Makoto Nagata, Masanori Takahashi, Noriyuki Miura, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Susceptibility evaluation of CAN transceiver circuits with in-place waveform capturing under RF DPI

Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, 2017, 2017 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMCCompo).

Evaluation of Undesired Radio Waves Below −170 dBm/Hz From Semiconductor Switching Devices for Impact on Wireless Communications

Makoto Nagata, Masahiro Yamaguchi, Noriyuki Miura, 2019, IEEE Letters on Electromagnetic Compatibility Practice and Applications.

Low-Power and Wideband Inductive-Coupling Communication for 3D Integration

Tadahiro Kuroda, Noriyuki Miura, 2008 .

On-chip substrate-bounce monitoring for laser-fault countermeasure

Tatsuya Fujii, Yu-ichi Hayashi, Makoto Nagata, 2016, 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST).

Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration

Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda, 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.

At-Product-Test Dedicated Adaptive supply-resonance suppression

Makoto Nagata, Noriyuki Miura, Taisuke Hayashi, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Tadahiro Kuroda, Yasuhisa Shimazaki, Noriyuki Miura, 2012, 2012 IEEE COOL Chips XV.

A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2020, ISCAS.

Physical authentication using side-channel information

Yu-ichi Hayashi, Takaaki Mizuki, Makoto Nagata, 2016, 2016 4th International Conference on Information and Communication Technology (ICoICT).

A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×

Tadahiro Kuroda, Noriyuki Miura, Mitsuko Saito, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2019, IEICE Trans. Electron..

Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection

Makoto Nagata, Wei He, Shivam Bhasin, 2016, 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Tadahiro Kuroda, Hideharu Amano, Kiichi Niitsu, 2009, 2009 Symposium on VLSI Circuits.

A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology

Tadahiro Kuroda, Takayasu Sakurai, Noriyuki Miura, 2006, IEICE Trans. Electron..

Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Makoto Ikeda, Noriyuki Miura, 2016, IEEE J. Solid State Circuits.

Proactive and reactive protection circuit techniques against EM leakage and injection

Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, 2015, 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC).

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

Yu-ichi Hayashi, Makoto Nagata, Takafumi Aoki, 2015, Journal of Cryptology.

A 30Gb/s/link 2.2Tb/s/mm2 inductively-coupled injection-locking CDR

Tadahiro Kuroda, Noriyuki Miura, Yasuhiro Take, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2012, IEEE Journal of Solid-State Circuits.

An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor

Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013, IEEE Micro.

Active crosstalk cancel for high-density inductive inter-chip wireless communication

Tadahiro Kuroda, Amit Kumar, Noriyuki Miura, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Circuit-level information leakage prevention for fault detection

Tatsuya Fujii, Yu-ichi Hayashi, Noriyuki Miura, 2016, 2016 URSI Asia-Pacific Radio Science Conference (URSI AP-RASC).

Practical methodology of post-layout gate sizing for 15% more power saving

Tadahiro Kuroda, Noriyuki Miura, Naoki Kato, 2004 .

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2013, ASP-DAC.

Re-examination of 1/f Noise in FD-SOI for Practical Usage of Analog Circuits

Anil Kumar, Noriyuki Miura, Hirotaka Komatsubara, 2006 .

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler

Tadahiro Kuroda, Hiroki Ishikuro, Noriyuki Miura, 2014, IEEE Journal of Solid-State Circuits.

Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus

Makoto Nagata, Hiroaki Ikeda, Noriyuki Miura, 2017 .

A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 1Tb/s 3W Inductive-Coupling Transceiver Chip

Tadahiro Kuroda, Noriyuki Miura, 2007, 2007 Asia and South Pacific Design Automation Conference.

A 500MHz-BW −52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013, 2013 IEEE Hot Chips 25 Symposium (HCS).

Evaluation of Near-Field Undesired Radio Waves from Semiconductor Switching Circuits

Makoto Nagata, Masahiro Yamaguchi, Noriyuki Miura, 2019, 2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE.

Superiority of In-Stack Decoupling Capacitor for 3D-LSI with Wide I/O Data Bus

Hiroaki Ikeda, Noriyuki Miura, Katsuya Kikuchi, 2016 .

A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar

Makoto Nagata, Noriyuki Miura, Daisuke Suzuki, 2019, ASHES@CCS.

A Simplified Dopant Pile-Up Model for Process Simulators(Regular Section)

Noriyuki Miura, Hirokazu Hayashi, Marie Mochizuki, 2002 .

Simultaneous data and power transmission using nested clover coils

Tadahiro Kuroda, Noriyuki Miura, Hayun Chung, 2012, 17th Asia and South Pacific Design Automation Conference.

Practical methodology of post-layout gate sizing for 15% more power saving

Tadahiro Kuroda, Noriyuki Miura, Naoki Kato, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking

Tadahiro Kuroda, Noriyuki Miura, Mitsuko Saito, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips

Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, 2014, 2014 IEEE 23rd Asian Test Symposium.

A 0.45V-to-2.7V inductive-coupling level shifter

Tadahiro Kuroda, Kiichi Niitsu, Noriyuki Miura, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking

Tadahiro Kuroda, Hiroki Ishikuro, Takayasu Sakurai, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 1 mm Pitch $80 \times 80$ Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan

Makoto Nagata, Takuji Miki, Daisuke Fujimoto, 2015, IEEE Journal of Solid-State Circuits.

Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor

Masanori Takahashi, Makoto Nagata, Noriyuki Miura, 2018, IEEE Journal of Solid-State Circuits.

Correlation power analysis using bit-level biased activity plaintexts against AES cores with countermeasures

Jean-Luc Danger, Makoto Nagata, Takafumi Aoki, 2014, 2014 International Symposium on Electromagnetic Compatibility, Tokyo.

A 1 TB/s 1 pJ/b 6.4 ${\rm mm}^{2}/{\rm TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

Tadahiro Kuroda, Noriyuki Miura, Mitsuko Saito, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis

Takeshi Sugawara, Makoto Nagata, Noriyuki Miura, 2017, 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Flush Code Eraser: Fast Attack Response Invalidating Cryptographic Sensitive Data

Tatsuya Fujii, Noriyuki Miura, Kazuo Sakiyama, 2020, IEEE Embedded Systems Letters.

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator

Satoru Takahashi, Atsushi Nakamura, Makoto Nagata, 2014, IEICE Trans. Electron..

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

Tadahiro Kuroda, Noriyuki Miura, Shusuke Kawai, 2011, IEEE Journal of Solid-State Circuits.

Digital rosetta stone: A sealed permanent memory with inductive-coupling power and data link

Tadahiro Kuroda, Hiroyuki Ochi, Noriyuki Miura, 2009, 2009 Symposium on VLSI Circuits.

Physical Attack Protection Techniques for IC Chip Level Hardware Security

Makoto Nagata, Takuji Miki, Noriyuki Miura, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure

Makoto Nagata, Noriyuki Miura, Daisuke Suzuki, 2021, J. Cryptogr. Eng..

Design and concept proof of an inductive impulse self-destructor in sense-and-react countermeasure against physical attacks

Makoto Nagata, Noriyuki Miura, Kazuo Sakiyama, 2021 .

Power-noise measurements of small-scale inverter chains

Kouji Ichikawa, Makoto Nagata, Noriyuki Miura, 2013, 2013 IEEE International Meeting for Future of Electron Devices, Kansai.

A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing

Makoto Nagata, Takuji Miki, Naoya Watanabe, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.