Sudipta Bhawmik

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An almost full-scan BIST solution-higher fault coverage and shorter test application time

Kwang-Ting Cheng, Huan-Chih Tsai, Sudipta Bhawmik, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

KIDLAN: a hardware description language

Sudipta Bhawmik, Anurag Acharya, C. R. K. Prasad, 1989 .

Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC

Krishnendu Chakrabarty, Sudipta Bhawmik, Ran Wang, 2015, ACM Trans. Design Autom. Electr. Syst..

Expert system to configure global design for testability structure in a VLSI circuit

Parimal Pal Chaudhuri, Sudipta Bhawmik, P. P. Chaudhuri, 1989, Microprocess. Microsystems.

Core Based ASIC Design

Sudipta Bhawmik, Frank P. Higgins, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Design of Testable VLSI Circuits with Minumum Area Overhead

Parimal Pal Chaudhuri, Sudipta Bhawmik, Anurag Acharya, 1989, IEEE Trans. Computers.

On improving test quality of scan-based BIST

Kwang-Ting Cheng, Huan-Chih Tsai, Sudipta Bhawmik, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A BIST scheme for the detection of path-delay faults

Nilanjan Mukherjee, Sudipta Bhawmik, Tapan J. Chakraborty, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Efficient test-point selection for scan-based BIST

Kwang-Ting Cheng, Chih-Jen Lin, Huan-Chih Tsai, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Introduction to SystemC

Sudipta Bhawmik, 2001, VLSI Design.

A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Niraj K. Jha, Sudipta Bhawmik, Indradeep Ghosh, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Integration of partial scan and built-in self-test

Yervant Zorian, Chih-Jen Lin, Sudipta Bhawmik, 1995, J. Electron. Test..

An integrated cad system for design of testable vlsi circuits

Sudipta Bhawmik, 1989 .

Enhanced controllability for IDDQ test sets using partial scan

Chih-Jen Lin, Sudipta Bhawmik, Tapan J. Chakraborty, 1991, 28th ACM/IEEE Design Automation Conference.

A hybrid algorithm for test point selection for scan-based BIST

Kwang-Ting Cheng, Chih-Jen Lin, Huan-Chih Tsai, 1997, DAC.

DFTEXPERT: an expert system for design of testable VLSI circuits

Parimal Pal Chaudhuri, Sudipta Bhawmik, P. P. Chaudhuri, 1988, IEA/AIE '88.

Using 3D-COSTAR for 2.5D test cost optimization

Erik Jan Marinissen, Said Hamdioui, Sudipta Bhawmik, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

A practical method for selecting partial scan flip-flops for large circuits

Sudipta Bhawmik, Indradeep Ghosh, 1997, Proceedings Tenth International Conference on VLSI Design.

At-speed interconnect testing and test-path optimization for 2.5D ICs

Krishnendu Chakrabarty, Sudipta Bhawmik, Ran Wang, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

KET—A Tool for Building Expert Systems

Sudipta Bhawmik, Parimal Palchaudhuri, P V Athawale, 1988 .

Impact of mid-bond testing in 3D stacked ICs

Erik Jan Marinissen, Said Hamdioui, Sudipta Bhawmik, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch

Dipanwita Roy Chowdhury, Sudipta Bhawmik, Subhayu Basu, 2002, J. Electron. Test..

Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach

Parimal Pal Chaudhuri, Sudipta Bhawmik, P. P. Chaudhuri, 1989, Integr..

A BIST scheme for RTL circuits based on symbolic testabilityanalysis

Niraj K. Jha, Sudipta Bhawmik, Indradeep Ghosh, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The P1500 DFT disclosure document: a standard to communicate mergeable core DFT data

Scott Davidson, Sudipta Bhawmik, Kamran Zarrineh, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs

Krishnendu Chakrabarty, Sudipta Bhawmik, Ran Wang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Automated Design For Testability (DFT) Tools for VLSI Circuits

Sudipta Bhawmik, Aloke K. Das, Parimal Palchaudhuri, 1988 .

PSBIST: A partial-scan based built-in self-test scheme

Yervant Zorian, Chih-Jen Lin, Sudipta Bhawmik, 1993, Proceedings of IEEE International Test Conference - (ITC).

Reformatting test patterns for testing embedded core based system using test access mechanism (TAM) switch [SoC]

Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

POWERTEST: a tool for energy conscious weighted random pattern testing

Kaushik Roy, Sudipta Bhawmik, Xiaodong Zhang, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Improving the test quality for scan-based BIST using a general test application scheme

Kwang-Ting Cheng, Huan-Chih Tsai, Sudipta Bhawmik, 1999, DAC '99.

Built-in self-test for interposer-based 2.5D ICs

Krishnendu Chakrabarty, Sudipta Bhawmik, Ran Wang, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Efficient characterisation of cellular automata

P. Pal Chaudhuri, Sudipta Bhawmik, Amit Das, 1990 .