S. Chhun

Aluminum charge/dipole passivation induced by hydrogen diffusion in high-k metal gate

D. Petit, G. Ribes, V. Barral, 2014, 2014 IEEE International Reliability Physics Symposium.

14nm FDSOI technology for high speed and energy efficient applications

J. Mazurier, O. Faynot, A. Pofelski, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Cu surface treatment influence on Si adsorption properties of CuSiN self-aligned barriers for sub-65nm technology node

S. Chhun, J. Michelon, L. Pinzelli, 2006 .

Integration of multi-level self-aligned CoWP barrier compatible with high performance BEOL

S. Chhun, M. Mellier, S. Jullian, 2006, 2006 International Interconnect Technology Conference.

High performance CMOS FDSOI devices activated at low temperature

J. Mazurier, G. Ghibaudo, P. Batude, 2016, 2016 IEEE Symposium on VLSI Technology.

Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes

L. Arnaud, S. Chhun, C. Besset, 2009, 2009 IEEE International Interconnect Technology Conference.

New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI

X. Garros, P. Batude, M. Vinet, 2014, 2014 IEEE International Electron Devices Meeting.

Characterization of electrical and crystallographic properties of metal layers at deca-nanometer scale using Kelvin probe force microscope

S. Chhun, A. Bajolet, Nicolas Gaillard, 2006 .

Optimization of signal propagation performances in interconnects of the 45 nm node by exhaustive analysis of the technological parameters impact

V. Arnal, J. Torres, B. Blampey, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..