K. Roy

发表

Tree-CNN: A hierarchical Deep Convolutional Neural Network for incremental learning

Priyadarshini Panda, Kaushik Roy, Deboleena Roy, 2018, Neural Networks.

Towards spike-based machine intelligence with neuromorphic computing

Kaushik Roy, Priyadarshini Panda, Akhilesh Jaiswal, 2019, Nature.

DIET-SNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks pdf

Kaushik Roy, Nitin Rathi, K. Roy, 2020, ArXiv.

Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation pdf

Kaushik Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, 2020, ICLR.

Antiferroelectric Tunnel Junctions as Energy-Efficient Coupled Oscillators: Modeling, Analysis, and Application to Solving Combinatorial Optimization Problems

K. Roy, Robert Andrawis, K. Roy, 2020, IEEE Transactions on Electron Devices.

Perspective: Stochastic magnetic devices for cognitive computing

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2018, Journal of Applied Physics.

Ising computation based combinatorial optimization using spin-Hall effect (SHE) induced stochastic magnetization reversal

Akhilesh R. Jaiswal, K. Roy, A. Jaiswal, 2017 .

Low-Power and testable circuit synthesis using Shannon decomposition

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2007, TODE.

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points

S. Bhunia, A. Raychowdhury, Swaroop Ghosh, 2005, European Test Symposium (ETS'05).

Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting

Kaushik Roy, Kon-Woo Kwon, Sri Harsha Choday, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Prospects of Thin-Film Thermoelectric Devices for Hot-Spot Cooling and On-Chip Energy Harvesting

Kaushik Roy, Mark S. Lundstrom, Sri Harsha Choday, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Sensitivity analysis and optimization of thin-film thermoelectric coolers

Kaushik Roy, Sri Harsha Choday, S. H. Choday, 2013 .

On-chip energy harvesting using thin-film thermoelectric materials

K. Roy, V. Raghunathan, S. H. Choday, 2013, 29th IEEE Semiconductor Thermal Measurement and Management Symposium.

Gabor filter assisted energy efficient fast learning Convolutional Neural Networks

Kaushik Roy, Priyadarshini Panda, Syed Shakib Sarwar, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

BiCMOS logic testing

Kaushik Roy, Jacob A. Abraham, Marc E. Levitt, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Saibal Mukhopadhyay, Kaushik Roy, Hamid Mahmoodi-Meimand, 2003, Proc. IEEE.

Delay fault localization in test-per-scan BIST using built-in delay sensor

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2005, 14th Asian Test Symposium (ATS'05).

Organismic materials for beyond von Neumann machines

Kai Wang, Yoav Kalcheim, Ivan K. Schuller, 2020 .

Design Space Exploration of Hysteresis-Free HfZrOx-Based Negative Capacitance FETs

Kaushik Roy, K. Roy, Ankit Sharma, 2017, IEEE Electron Device Letters.

The Effects of Direct Source-to-Drain Tunneling and Variation in the Body Thickness on (100) and (110) Sub-10-nm Si Double-Gate Transistors

K. Roy, W. Cho, K. Roy, 2015, IEEE Electron Device Letters.

Energy efficient 'in memory' computing to enable decentralised service workflow composition in support of multi-domain operations

Kaushik Roy, Ian Taylor, Abbas Rahimi, 2021, Defense + Commercial Sensing.

In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology

Kaushik Roy, Akhilesh Jaiswal, Mustafa F. Ali, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Gradient Projection Memory for Continual Learning pdf

Kaushik Roy, Gobinda Saha, Isha Garg, 2021, ICLR.

SPACE: Structured Compression and Sharing of Representational Space for Continual Learning

Aayush Ankit, Gobinda Saha, Isha Garg, 2020, IEEE Access.

Tree-CNN: A Deep Convolutional Neural Network for Lifelong Learning

P. Panda, Deboleena Roy, K. Roy, 2018, ArXiv.

Deep Spiking Convolutional Neural Network Trained With Unsupervised Spike-Timing-Dependent Plasticity

Gopalakrishnan Srinivasan, Priyadarshini Panda, Chankyu Lee, 2019, IEEE Transactions on Cognitive and Developmental Systems.

Training Deep Spiking Convolutional Neural Networks With STDP-Based Unsupervised Pre-training Followed by Supervised Fine-Tuning

Gopalakrishnan Srinivasan, Priyadarshini Panda, Chankyu Lee, 2018, Front. Neurosci..

Going Deeper in Spiking Neural Networks: VGG and Residual Architectures

Kaushik Roy, Abhronil Sengupta, Robert Wang, 2018, Front. Neurosci..

Conditional Deep Learning for energy-efficient and enhanced pattern recognition

Kaushik Roy, Priyadarshini Panda, Abhronil Sengupta, 2015, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses

Pedro P. Irazoqui, Kaushik Roy, Sumeet Kumar Gupta, 2011 .

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

K. Roy, J.P. Kulkarni, K. Kim, 2007, IEEE Journal of Solid-State Circuits.

Layout-aware optimization of stt mrams

Kaushik Roy, Sumeet Kumar Gupta, Sang Phill Park, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

Patrick Ndai, Ashish Goel, Jing Li, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Quality programmable vector processors for approximate computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

SALSA: Systematic logic synthesis of approximate circuits

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2012, DAC Design Automation Conference 2012.

IMPACT: IMPrecise adders for low-power approximate computing

Kaushik Roy, Anand Raghunathan, Vaibhav Gupta, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Low-Power Digital Signal Processing Using Approximate Adders

Kaushik Roy, Anand Raghunathan, Vaibhav Gupta, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000, ISLPED '00.

Design Space and Memory Technology Co-exploration for In-Memory Computing Based Machine Learning Accelerators

K. Roy, I. Chakraborty, Cheng Wang, 2022, 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Smart cameras everywhere: AI vision on edge with emerging memories

Georgios Ch. Sirakoulis, Kaushik Roy, Alex James, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

B.C. Paul, K. Roy, A. Bansal, 2005, IEEE Transactions on Electron Devices.

One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency pdf

Kaushik Roy, Sayeed Shafayet Chowdhury, Nitin Rathi, 2021, ArXiv.

Area Efficient ROM-Embedded SRAM Cache

Kaushik Roy, Dongsoo Lee, K. Roy, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture

Kaushik Roy, Anand Raghunathan, Sumeet Kumar Gupta, 2012, DAC Design Automation Conference 2012.

Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors

Kaushik Roy, Dongsoo Lee, Jae-Joon Kim, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Column-selection-enabled 8T SRAM array with

Dongsoo Lee, Jae-Joon Kim, Sang Phill Park, 2011, ISLPED 2011.

Tolerance to Small Delay Defects by Adaptive Clock Stretching

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, 14th Asian Test Symposium (ATS'05).

Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, 11th IEEE International On-Line Testing Symposium.

A power-aware GALS architecture for real-time algorithm-specific tasks

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, Sixth international symposium on quality electronic design (isqed'05).

Statistical modeling of pipeline delay and design of pipeline under process variation to enhance yield in sub-100nm technologies

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, Design, Automation and Test in Europe.

A novel fault tolerant cache to improve yield in nanometer technologies

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Exploring high bandwidth pipelined cache architecture for scaled technology

T. N. Vijaykumar, A. Agarwal, K. Roy, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

DRG-cache: a data retention gated-ground cache for low power

K. Roy, Hai Li, A. Agarwal, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

A process-tolerant cache architecture for improved yield in nanoscale technologies

Kaushik Roy, Amit Agarwal, Animesh Datta, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Kaushik Roy, Bipul C. Paul, B. Paul, 2006, J. Electron. Test..

MRPF: an architectural transformation for synthesis of high-performance and low-power digital filters

Kaushik Roy, Hunsoo Choo, Khurram Muhammad, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters

Kaushik Roy, Khurram Muhammad, K. Muhammad, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

Kaushik Roy, Khurram Muhammad, K. Roy, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Models and algorithms for bounds on leakage in CMOS circuits

Mark C. Johnson, Kaushik Roy, Dinesh Somasekhar, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference

Dejan S. Milojicic, Kaushik Roy, Paolo Faraboschi, 2019, ASPLOS.

Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning

Dejan S. Milojicic, Kaushik Roy, Paolo Faraboschi, 2018, 2018 IEEE International Conference on Rebooting Computing (ICRC).

Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars

Indranil Chakraborty, Kaushik Roy, Deboleena Roy, 2017, IEEE Transactions on Emerging Topics in Computational Intelligence.

Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic

K. Roy, I. Chakraborty, Crossbars, 2017 .

Deep Spiking Neural Network: Energy Efficiency Through Time Based Coding

Kaushik Roy, Bing Han, K. Roy, 2020, ECCV.

Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity

Kaushik Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, 2020, 2020 International Joint Conference on Neural Networks (IJCNN).

Enabling Spike-Based Backpropagation for Training Deep Neural Network Architectures

Kaushik Roy, Chankyu Lee, Syed Shakib Sarwar, 2019, Frontiers in Neuroscience.

ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing

Kaushik Roy, Gopalakrishnan Srinivasan, K. Roy, 2019, Front. Neurosci..

STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing

Kaushik Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, 2018, ACM J. Emerg. Technol. Comput. Syst..

Cross-Layer Design Exploration for Energy-Quality Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks

Kaushik Roy, Abhronil Sengupta, Bing Han, 2018, IEEE Transactions on Multi-Scale Computing Systems.

SpiLinC: Spiking Liquid-Ensemble Computing for Unsupervised Speech and Image Recognition

Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy, 2018, Front. Neurosci..

An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain

Parami Wijesinghe, Kaushik Roy, Abhronil Sengupta, 2017, IEEE Transactions on Emerging Topics in Computational Intelligence.

An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain pdf

Kaushik Roy, Parami Wijesinghe, Abhronil Sengupta, 2017, ArXiv.

Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks pdf

Kaushik Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, 2017, ArXiv.

Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition

Kaushik Roy, Priyadarshini Panda, K. Roy, 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks

Kaushik Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons

Kaushik Roy, Parami Wijesinghe, Priyadarshini Panda, 2015, Scientific Reports.

Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-Linear Activations

Kaushik Roy, Priyadarshini Panda, Saima Sharmin, 2020, ECCV.

Spike-FlowNet: Event-based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks

Kostas Daniilidis, K. Roy, A. Z. Zhu, 2020, ECCV.

A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks

Priyadarshini Panda, Chankyu Lee, Kaushik Roy, 2019, 2019 International Joint Conference on Neural Networks (IJCNN).

A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability

Kaushik Roy, Pedro P. Irazoqui, Shriram Raghunathan, 2012, ISLPED '12.

A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications

Pedro P. Irazoqui, Kaushik Roy, Shriram Raghunathan, 2010, Journal of Neuroscience Methods.

Skyrmion Sensor-Based Low-Power Global Interconnects

K. Roy, Z. Al Azim, Mei-Chin Chen, 2017, IEEE Transactions on Magnetics.

Efficiency attacks on spiking neural networks

A. Raghunathan, Sarada Krithivasan, Nitin Rathi, 2022, DAC.

Biased Random Walk Using Stochastic Switching of Nanomagnets: Application to SAT Solver

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2018, IEEE Transactions on Electron Devices.

GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks

Kaushik Roy, Mustafa Fayez Ali, Aayush Ankit, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Low-power scan design using first-level supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SYCLOP: synthesis of CMOS logic for low power applications

Kaushik Roy, Sharat Prasad, S. Prasad, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Very Low-Complexity Digital Filters Based On Computational Redundancy Reduction

Kaushik Roy, Khurram Muhammad, K. Muhammad, 1999 .

Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Roadmap of Spin–Orbit Torques

Kang L. Wang, K. Roy, Hyunsoo Yang, 2021, IEEE Transactions on Magnetics.

Designing approximate circuits using clock overgating

Younghoon Kim, Kaushik Roy, Anand Raghunathan, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Voltage over-scaling: A cross-layer design perspective for energy efficient systems

Kaushik Roy, Georgios Karakonstantis, G. Karakonstantis, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches

Xuanyao Fong, Kaushik Roy, Xuanyao Fong, 2013, 2013 5th IEEE International Memory Workshop.

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications

Kaushik Roy, Jing Li, Kunhyuk Kang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Self-Consistent Electrothermal Model for Analyzing NBTI Effect in p-Type Poly-Si Thin-Film Transistors

Chih-Hsiang Ho, K. Roy, G. Panagopoulos, 2013, IEEE Transactions on Electron Devices.

Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2012, 2012 25th International Conference on VLSI Design.

Analysis and design of ultra low power thermoelectric energy harvesting systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Constructing energy-efficient mixed-precision neural networks through principal component analysis for edge intelligence

I. Chakraborty, Aayush Ankit, Deboleena Roy, 2019, Nature Machine Intelligence.

Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition pdf

Kaushik Roy, Priyadarshini Panda, K. Roy, 2016, ArXiv.

Analog Approach to Constraint Satisfaction Enabled by Spin Orbit Torque Magnetic Tunnel Junctions

C. Liyanagedera, Parami Wijesinghe, K. Roy, 2018, Scientific Reports.

Exploring variability and reliability of multi-level STT-MRAM cells

K. Roy, C. Augustine, G. Panagopoulos, 2012, Device Research Conference.

Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Kaushik Roy, Anand Raghunathan, Xuanyao Fong, 2016, Proceedings of the IEEE.

Multilevel Spin-Orbit Torque MRAMs

Xuanyao Fong, Kaushik Roy, Mei-Chin Chen, 2015, IEEE Transactions on Electron Devices.

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives

Kaushik Roy, Karthik Yogendra, Anand Raghunathan, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Stochastic Spiking Neural Networks Enabled by Magnetic Tunnel Junctions: From Nontelegraphic to Telegraphic Switching Regimes

Kaushik Roy, Chamika M. Liyanagedera, Abhronil Sengupta, 2017 .

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2015, IEEE Transactions on Biomedical Circuits and Systems.

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2014, IEEE Transactions on Neural Networks and Learning Systems.

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

Xuanyao Fong, Kaushik Roy, Charles Augustine, 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

Perovskite neural trees

M. Ge, Hanfei Yan, K. Roy, 2020, Nature Communications.

A CMOS thermal sensor and its applications in temperature adaptive design

Kaushik Roy, Mesut Meterelliyoz, Qikai Chen, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Minimizing ohmic loss in future processor IR events

Kaushik Roy, Mark M. Budnik, M. Budnik, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Power supply noise-aware scheduling and allocation for DSP synthesis

Yiran Chen, Kaushik Roy, Dongku Kang, 2005, Sixth international symposium on quality electronic design (isqed'05).

Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis

Kaushik Roy, Shreyas Sen, Priyadarshini Panda, 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Simultaneous multiple-V/sub dd/ scheduling and allocation for partitioned floorplan

Mark C. Johnson, Kaushik Roy, Dongku Kang, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Multiple-V/sub dd/ scheduling/allocation for partitioned floorplan

Mark C. Johnson, Kaushik Roy, Dongku Kang, 2003, Proceedings 21st International Conference on Computer Design.

Datapath scheduling with multiple supply voltages and level converters

Mark C. Johnson, Kaushik Roy, K. Roy, 1997, TODE.

Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing pdf

Kaushik Roy, Abhronil Sengupta, K. Roy, 2017, ArXiv.

STDP Based Unsupervised Multimodal Learning With Cross-Modal Processing in Spiking Neural Networks

Kaushik Roy, Nitin Rathi, K. Roy, 2021, IEEE Transactions on Emerging Topics in Computational Intelligence.

On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

Kaushik Roy, Liqiong Wei, Zhanping Chen, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

I/sub DD/ waveforms analysis for testing of domino and low voltage static CMOS circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Fault Detection and Location Using IDD Waveform Analysis

Kaushik Roy, Khurram Muhammad, K. Muhammad, 2001, IEEE Des. Test Comput..

The Applicability of IDD Waveform Analysis to Testing of CMOS Circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1997 .

Fast, low power evaluation of elementary functions using radial basis function networks

Kaushik Roy, Parami Wijesinghe, Chamika M. Liyanagedera, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Design of voltage-scalable meta-functions for approximate computing

Kaushik Roy, Anand Raghunathan, Debabrata Mohapatra, 2011, 2011 Design, Automation & Test in Europe.

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

Kaushik Roy, Debabrata Mohapatra, Ik Joon Chang, 2011, IEEE Transactions on Circuits and Systems for Video Technology.

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

Kaushik Roy, Jongsun Park, Ik Joon Chang, 2010, IET Circuits Devices Syst..

Realistic spin-FET performance assessment for reconfigurable logic circuits

Kaushik Roy, Dmitri E. Nikonov, Charles Augustine, 2010, 2010 Symposium on VLSI Technology.

Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis

Kaushik Roy, Elena I. Vatajelu, Georgios Panagopoulos, 2010, 2010 15th IEEE European Test Symposium.

Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy

Kaushik Roy, Arijit Raychowdhury, Sumeet Kumar Gupta, 2009 .

O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

Kaushik Roy, Swaroop Ghosh, Pooja Batra, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Fine-Grained Redundancy in Adders

Kaushik Roy, Patrick Ndai, Shih-Lien Lu, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits

S. Mukhopadhyay, H. Mahmoodi-Meimand, K. Roy, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Ultra-low-power DLMS adaptive filter for hearing aid applications

Kaushik Roy, Hendrawan Soeleman, Chris Hyung-Il Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

LALM: a logic-aware layout methodology to enhance the noise immunity of domino circuits

Kaushik Roy, Yonghee Im, K. Roy, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Ultra-low power DLMS adaptive filter for hearing aid applications

K. Roy, C. Kim, K. Roy, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

Reducing leakage in a high-performance deep-submicron instruction cache

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A NewParadigm forLow-power, Variation-Tolera nt Circuit Synthesis UsingCritical PathIsolation

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2006 .

An Energy-Efficient High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2001 .

Evaluating Opportunity and Effectiveness of Cache Resizing in Reducing Energy Dissipation

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001 .

Efficient power conversion for ultra low voltage micro scale energy transducers

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Spin-Orbit-Torque-Based Spin-Dice: A True Random-Number Generator

Kaushik Roy, Xuanyao Fong, Yusung Kim, 2015, IEEE Magnetics Letters.

Distance Computation Based on Coupled Spin-Torque Oscillators: Application to Image Processing

Wolfgang Porod, Kaushik Roy, Minsuk Koo, 2020, Physical Review Applied.

Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction

Kaushik Roy, Bing Han, Abhronil Sengupta, 2016, IEEE Transactions on Electron Devices.

Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives

Kaushik Roy, Abhronil Sengupta, K. Roy, 2018 .

Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power supply noise aware floorplanning and decoupling capacitance placement

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

The design and hardware implementation of a low-power real-time seizure detection algorithm

Kaushik Roy, Robert M Worth, Shriram Raghunathan, 2009, Journal of neural engineering.

Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies

Kaushik Roy, Chamika M. Liyanagedera, Minsuk Koo, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Magnetoelectric oxide based stochastic spin device towards solving combinatorial optimization problems

Kaushik Roy, Yong Shim, Saima Sharmin, 2017, Scientific Reports.

Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001 .

Exploring Spin Transfer Torque Devices for Unconventional Computing

Kaushik Roy, Mrigank Sharad, Xuanyao Fong, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses pdf

Kaushik Roy, Abhronil Sengupta, K. Roy, 2015, ArXiv.

Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets pdf

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2015, ArXiv.

DIET-SNN: A Low-Latency Spiking Neural Network With Direct Input Encoding and Leakage and Threshold Optimization

K. Roy, Nitin Rathi, K. Roy, 2021, IEEE Transactions on Neural Networks and Learning Systems.

Design and Comparative Analysis of Spintronic Memories Based on Current and Voltage Driven Switching

Robert Andrawis, Kaushik Roy, Akhilesh Jaiswal, 2018, IEEE Transactions on Electron Devices.

Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization

Kaushik Roy, Akhilesh Jaiswal, Yong Shim, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning

Kaushik Roy, Gopalakrishnan Srinivasan, Abhronil Sengupta, 2016, Scientific Reports.

Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing

Kaushik Roy, Abhronil Sengupta, K. Roy, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

Spin Orbit Torque Based Electronic Neuron pdf

Kaushik Roy, Abhronil Sengupta, Yusung Kim, 2014, ArXiv.

A hybrid spin-charge mixed-mode simulation framework for evaluating STT-MRAM bit-cells utilizing multiferroic tunnel junctions

Xuanyao Fong, K. Roy, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances

J. Tschanz, V. De, K. Roy, 2011, IEEE Transactions on Electron Devices.

Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions

K. Roy, D. Nikonov, N. Mojumder, 2010 .

Self-Consistent Transport-Magnetic Simulation and Benchmarking of Hybrid Spin-Torque Driven Magnetic Tunnel Junctions (MTJs)

K. Roy, N. Mojumder, C. Augustine, 2010, 2010 18th Biennial University/Government/Industry Micro/Nano Symposium.

Gate leakage reduction for scaled devices using transistor stacking

Kaushik Roy, Amit Agarwal, Chris H. Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks

B. Chakrabarti, W. Haensch, K. Roy, 2022, ArXiv.

RMP-SNN: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Network

K. Roy, Bing Han, G. Srinivasan, 2020, 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

Injection-Locked Spin Hall-Induced Coupled-Oscillators for Energy Efficient Associative Computing

K. Roy, M. Sharad, Deliang Fan, 2015, IEEE Transactions on Nanotechnology.

PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design

Kaushik Roy, Maryam Parsa, Aayush Ankit, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Noise resilient leaky integrate-and-fire neurons based on multi-domain spintronic devices

K. Roy, Chankyu Lee, Cheng Wang, 2022, Scientific Reports.

Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays

Kaushik Roy, Amogh Agrawal, Tanvi Sharma, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Multi-Level Neuromorphic Devices Built on Emerging Ferroic Materials: A Review

Kaushik Roy, Amogh Agrawal, Eunseon Yu, 2021, Frontiers in Neuroscience.

Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges

Kaushik Roy, Indranil Chakraborty, Anand Raghunathan, 2020, Proceedings of the IEEE.

Topological semi-metal Na3Bi as efficient spin injector in current driven magnetic tunnel junction

K. Roy, A. K. Reza, K. Roy, 2019 .

Magnetic Skyrmion as a Spintronic Deep Learning Spiking Neuron Processor

Kaushik Roy, Mei-Chin Chen, Abhronil Sengupta, 2018, IEEE Transactions on Magnetics.

High-Density SOT-MRAM Based on Shared Bitline Structure

Kaushik Roy, Yeongkyo Seo, K. Roy, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency pdf

Kaushik Roy, Indranil Chakraborty, Zubair Al Azim, 2018, ArXiv.

Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM

Arnab Raha, Vijay Raghunathan, Kaushik Roy, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime pdf

Kaushik Roy, Chamika M. Liyanagedera, Abhronil Sengupta, 2017, ArXiv.

Magnetic Tunnel Junction as an On-Chip Temperature Sensor

K. Roy, Abhronil Sengupta, B. Jung, 2017, Scientific Reports.

Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference

Kaushik Roy, Shuhan Chen, Abhronil Sengupta, 2017, Scientific Reports.

Spin-torque sensors with differential signaling for fast and energy efficient global interconnects

Kaushik Roy, Zubair Azim, Z. Azim, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Kaushik Roy, Anand Raghunathan, Sachin S. Sapatnekar, 2017, DAC.

Image segmentation with stochastic magnetic tunnel junctions and spiking neurons

Kaushik Roy, Parami Wijesinghe, Chamika M. Liyanagedera, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Magnetic Skyrmions for Cache Memory

K. Roy, Mei-Chin Chen, K. Roy, 2017, 1705.01095.

A Vision for All-Spin Neural Networks: A Device to System Perspective

Abhronil Sengupta, Kaushik Roy, K. Roy, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Area-Efficient SOT-MRAM With a Schottky Diode

Kaushik Roy, Yeongkyo Seo, Kon-Woo Kwon, 2016, IEEE Electron Device Letters.

High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM

Kaushik Roy, Xuanyao Fong, Yeongkyo Seo, 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure-Based Memory

Kaushik Roy, Xuanyao Fong, Ahmed Kamal Reza, 2016, IEEE Transactions on Electron Devices.

Spin-Torque Sensors for Energy Efficient High-Speed Long Interconnects

Kaushik Roy, Syed Shakib Sarwar, Abhronil Sengupta, 2015, IEEE Transactions on Electron Devices.

Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity pdf

Kaushik Roy, Xuanyao Fong, Abhronil Sengupta, 2014, ArXiv.

SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

Xuanyao Fong, Kaushik Roy, Yusung Kim, 2014, IEEE Electron Device Letters.

DSH-MRAM: Differential Spin Hall MRAM for On-Chip Memories

S. H. Choday, Yusung Kim, K. Roy, 2013, IEEE Electron Device Letters.

Efficient Neuromorphic Systems and Emerging Technologies: Prospects and Perspectives

Kaushik Roy, Abhronil Sengupta, Aayush Ankit, 2017 .

On-Chip Non-volatile STT-MRAM for Zero-Standby Power

Xuanyao Fong, Kaushik Roy, Xuanyao Fong, 2017 .

Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects

Kaushik Roy, Zubair Al Azim, Ankit Sharma, 2017, IEEE Magnetics Letters.

Robust and Cascadable Nonvolatile Magnetoelectric Majority Logic

Kaushik Roy, Akhilesh Jaiswal, Amogh Agrawal, 2017, IEEE Transactions on Electron Devices.

Design of Sigma–Delta Modulators With Arbitrary Transfer Functions

Kaushik Roy, Khurram Muhammad, Yongtao Wang, 2007, IEEE Transactions on Signal Processing.

Design of sigma-delta modulators with arbitrary transfer functions

Kaushik Roy, Khurram Muhammad, Yongtao Wang, 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2007, Microelectron. J..

Modeling and Analysis of Leakage Currents in Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2005, Sixth international symposium on quality electronic design (isqed'05).

Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications

Kaushik Roy, Anand Raghunathan, A. Raghunathan, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization

Kaushik Roy, Priyadarshini Panda, Sai Aparna Aketi, 2019, ArXiv.

RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks

Kaushik Roy, Amogh Agrawal, Mustafa Ali, 2020, ISLPED.

Control of current saturation and threshold voltage shift in indium oxide nanowire transistors with femtosecond laser annealing.

M. Qi, K. Roy, P. Srisungsitthisunti, 2011, ACS nano.

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Kaushik Roy, Amogh Agrawal, Sangamesh Kodge, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Kaushik Roy, Akhilesh Jaiswal, Amogh Agrawal, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

R-MRAM: A ROM-Embedded STT MRAM Cache

Xuanyao Fong, Kaushik Roy, Dongsoo Lee, 2013, IEEE Electron Device Letters.

Roadmap on emerging hardware and technology for machine learning

Kaushik Roy, Yuchao Yang, Alberto Salleo, 2020, Nanotechnology.

8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Kaushik Roy, Indranil Chakraborty, Akhilesh Jaiswal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Micro-scale energy harvesting: A system design perspective

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

TREND: Transferability-Based Robust ENsemble Design pdf

Kaushik Roy, Deepak Ravikumar, Sangamesh Kodge, 2020, IEEE Transactions on Artificial Intelligence.

Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits

K. Roy, V.K. De, A. Raychowdhury, 2009, IEEE Transactions on Electron Devices.

Nano Spiral Inductors for Low-Power Digital Spintronic Circuits

J. Kulkarni, C. Augustine, B. Jung, 2010, IEEE Transactions on Magnetics.

Reliability- and Process-Variation Aware Design of VLSI Circuits

B.C. Paul, K. Roy, M. Alam, 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Efficient modeling of 1/f/sup /spl alpha// noise using multirate process

K. Roy, Jongsun Park, K. Muhammad, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Low Effort Approach to Structured CNN Design Using PCA

Kaushik Roy, Priyadarshini Panda, Isha Garg, 2018, IEEE Access.

Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance

V. De, A. Keshavarzi, A. Raychowdhury, 2006, Device Research Conference.

Habituation based synaptic plasticity and organismic learning in a quantum perovskite

K. Roy, C. Mazzoli, S. Ramanathan, 2017, Nature Communications.

Carbon-nanotube-based voltage-mode multiple-valued logic design

K. Roy, A. Raychowdhury, K. Roy, 2005, IEEE Transactions on Nanotechnology.

Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers pdf

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2013, ArXiv.

Coupled Spin Torque Nano Oscillators for Low Power Neural Computation

Kaushik Roy, Karthik Yogendra, Deliang Fan, 2015, IEEE Transactions on Magnetics.

Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions

Kaushik Roy, Akhilesh Jaiswal, Saima Sharmin, 2016, IEEE Transactions on Electron Devices.

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation

Jing Li, K. Roy, A. Bansal, 2007, IEEE Transactions on Electron Devices.

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era

Kaushik Roy, Swaroop Ghosh, K. Roy, 2010, Proceedings of the IEEE.

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Thermoelectric Spin-Transfer Torque MRAM with Sub-Nanosecond Bi-Directional Writing using Magnonic Current

K. Roy, D. Abraham, N. Mojumder, 2011, 1108.2386.

Magnonic Spin-Transfer Torque MRAM With Low Power, High Speed, and Error-Free Switching

K. Roy, D. Abraham, D. Worledge, 2011, IEEE Transactions on Magnetics.

Thermoelectric Spin-Transfer Torque MRAM With Fast Bidirectional Writing Using Magnonic Current

K. Roy, D. Abraham, N. Mojumder, 2013, IEEE Transactions on Magnetics.

Low power reconfigurable DCT design based on sharing multiplication

Kaushik Roy, Jongsun Park, Soonkeon Kwon, 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Leakage Current in Deep-Submicron CMOS Circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2002, J. Circuits Syst. Comput..

Nanometer scale technologies: device considerations

K. Roy, A. Raychowdhury, K. Roy, 2004 .

MACACO: Modeling and analysis of circuits for approximate computing

Kaushik Roy, Amit Agarwal, Anand Raghunathan, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack

Kaushik Roy, Mei-Chin Chen, Ashish Ranjan, 2019, IEEE Transactions on Magnetics.

Energy-Efficient and Improved Image Recognition with Conditional Deep Learning

Kaushik Roy, Priyadarshini Panda, Abhronil Sengupta, 2017, ACM J. Emerg. Technol. Comput. Syst..

Towards Understanding the Effect of Leak in Spiking Neural Networks pdf

Kaushik Roy, Chankyu Lee, Sayeed Shafayet Chowdhury, 2020, Neurocomputing.

Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal

Kaushik Roy, Karthik Yogendra, Minsuk Koo, 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Magnetic Pattern Recognition Using Injection-Locked Spin-Torque Nano-Oscillators

Kaushik Roy, Karthik Yogendra, Byunghoo Jung, 2016, IEEE Transactions on Electron Devices.

Neural Computing With Magnetoelectric Domain-Wall-Based Neurosynaptic Devices

Kaushik Roy, Priyadarshini Panda, Amogh Agrawal, 2021, IEEE Transactions on Magnetics.

Design of a Low-Voltage Analog-to-Digital Converter Using Voltage-Controlled Stochastic Switching of Low Barrier Nanomagnets

Kaushik Roy, Indranil Chakraborty, Amogh Agrawal, 2018, IEEE Magnetics Letters.

A non-volatile cascadable magneto-electric material implication logic

Kaushik Roy, Akhilesh Jaiswal, Indranil Chakraborty, 2017, 2017 75th Annual Device Research Conference (DRC).

Voltage-Driven Domain-Wall Motion based Neuro-Synaptic Devices for Dynamic On-line Learning

Kaushik Roy, Priyadarshini Panda, Amogh Agrawal, 2017 .

Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion pdf

Kaushik Roy, Akhilesh Jaiswal, Amogh Agrawal, 2017, ArXiv.

Proposal for a Leaky-Integrate-Fire Spiking Neuron Based on Magnetoelectric Switching of Ferromagnets

Kaushik Roy, Gopalakrishnan Srinivasan, Akhilesh Jaiswal, 2016, IEEE Transactions on Electron Devices.

Coupled Spin-Torque Nano-Oscillator-Based Computation

Kaushik Roy, Karthik Yogendra, Chamika M. Liyanagedera, 2017, ACM J. Emerg. Technol. Comput. Syst..

Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Ultra-Low power neuromorphic computing with spin-torque devices

Karthik Yogendra, Mrigank Sharad, Kaushik Roy, 2013, 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks

Kaushik Roy, Parami Wijesinghe, Gopalakrishnan Srinivasan, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Perovskite nickelates as bio-electronic interfaces

Kaushik Roy, Gobinda Saha, Hua Zhou, 2019, Nature Communications.

Cross‐Hierarchy Design Exploration for Implantable Electronics

Kaushik Roy, Mrigank Sharad, M. Sharad, 2014 .

Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators

Kaushik Roy, Indranil Chakraborty, Aayush Ankit, 2020, IEEE Micro.

A circuit-compatible model of ballistic carbon nanotube field-effect transistors

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A high density, carbon nanotube capacitor for decoupling applications

Kaushik Roy, Arijit Raychowdhury, Aditya Bansal, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Convolving over time via recurrent connections for sequential weight sharing in neural networks

Kaushik Roy, Jason M. Allred, K. Roy, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2005, TODE.

Integer linear programming-based synthesis of skewed logic circuits

Cheng-Kok Koh, N. Sirisantana, K. Roy, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Synthesis of selectively clocked skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2002, Proceedings International Symposium on Quality Electronic Design.

Low-Power CMOS VLSI Circuit Design

Kaushik Roy, Sharat Prasad, K. Roy, 2000 .

Multiple scan chain design technique for power reduction during test application in BIST

Kaushik Roy, Swarup Bhunia, Debjyoti Ghosh, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Computing in Memory With Spin-Transfer Torque Magnetic RAM

Anand Raghunathan, Kaushik Roy, Ashish Ranjan, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Power reduction in test-per-scan BIST

Kaushik Roy, Xiaodong Zhang, K. Roy, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).