Paul S. Andry

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

Paul S. Andry, Cornelia K. Tsang, Bucknell C. Webb, 2008, IBM J. Res. Dev..

3D chip stacking with C4 technology

Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, 2008, IBM J. Res. Dev..

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, 2008, IBM J. Res. Dev..

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Keith A. Jenkins, Alina Deutsch, Paul S. Andry, 2005, IBM J. Res. Dev..

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Yong Liu, Xiaoxiong Gu, Herschel A. Ainspan, 2012, IEEE Journal of Solid-State Circuits.

An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors

Luca P. Carloni, Kenneth L. Shepard, Paul S. Andry, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Three-dimensional silicon integration

Katsuyuki Sakuma, Anna W. Topol, Paul S. Andry, 2008, IBM J. Res. Dev..

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

Paul S. Andry, Cornelia K. Tsang, Edmund J. Sprogis, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Driving large-sized OLED TVs with an amorphous-silicon backplane

Paul S. Andry, Frank R. Libsch, Takatoshi Tsujimura, 2005 .