Zhiru Zhang

发表

T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations

Nitish Srivastava, Hongbo Rong, Guanyu Feng, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A reconfigurable analog substrate for highly efficient maximum flow computation

Zhiru Zhang, Gai Liu, Zhiru Zhang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Predictable accelerator design with time-sensitive affine types

Zhiru Zhang, Rachit Nigam, Sachille Atapattu, 2020, PLDI.

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation

Zhiru Zhang, Chang Xu, Guojie Luo, 2017, FPGA.

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization pdf

Azadeh Davoodi, Zhiru Zhang, Sergio Bampi, 2020, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization

Jason Cong, Zhiru Zhang, Bin Liu, 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

DA systemization of knowledge: A catalog of prior forward-looking initiatives

Gang Qu, Zhiru Zhang, Farinaz Koushanfar, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling

Zhiru Zhang, David H. Albonesi, Abhinandan Majumdar, 2016, 2016 ACM/IEEE 7th International Conference on Cyber-Physical Systems (ICCPS).

A-QED Verification of Hardware Accelerators

Jason Cong, Zhiru Zhang, Peng Wei, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs

Jason Cong, Jie Wang, Yun Liang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Session details: Technical Session 5: Processors and Accelerators

Zhiru Zhang, Zhiru Zhang, 2015, Symposium on Field Programmable Gate Arrays.

Replication Package for Article: Predictable Accelerator Design with Time-Sensitive Affine types

Zhiru Zhang, Zhijing Li, Rachit Nigam, 2020, Artifact Digital Object Group.

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

Christopher Torng, Khalid Al-Hawaj, Christopher Batten, 2019, IEEE Solid-State Circuits Letters.

Bit-level optimization for high-level synthesis and FPGA-based acceleration

Jason Cong, Zhiru Zhang, Sheng Zhou, 2010, FPGA '10.

Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating

Zhiru Zhang, Christopher De Sa, G. Edward Suh, 2019, MICRO.

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Behavior and communication co-optimization for systems with sequential communication media

Jason Cong, Zhiru Zhang, Wei Jiang, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

ElasticFlow: A complexity-effective approach for pipelining irregular loop nests

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Gradual Relaxation Techniques with Applications to Behavioral Synthesis

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2003, ICCAD 2003.

An efficient and versatile scheduling algorithm based on SDC formulation

Jason Cong, Zhiru Zhang, J. Cong, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

CASA: Correlation-aware speculative adders

Zhiru Zhang, Ye Tao, Gai Liu, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Area-efficient pipelining for FPGA-targeted high-level synthesis

Zhiru Zhang, Ritchie Zhao, Mingxing Tan, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Improving Neural Network Quantization without Retraining using Outlier Channel Splitting pdf

Zhiru Zhang, Christopher De Sa, Yuwei Hu, 2019, ICML.

DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only)

Zhiru Zhang, Chang Xu, Guojie Luo, 2018, FPGA.

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis

Shreesha Srinath, Christopher Batten, Zhiru Zhang, 2017, FPGA.

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Zhiru Zhang, Udit Gupta, Mingxing Tan, 2015, FPGA.

Challenges and opportunities of ESL design automation

Zhiru Zhang, Deming Chen, Deming Chen, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product

Nitish Srivastava, Zhiru Zhang, David Albonesi, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Application-specific instruction generation for configurable processor architectures

Jason Cong, Zhiru Zhang, Yiping Fan, 2004, FPGA '04.

PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization

Zhiru Zhang, Gai Liu, 2019, ACM Trans. Reconfigurable Technol. Syst..

High-Level Synthesis with Timing-Sensitive Information Flow Enforcement

Zhiru Zhang, G. Edward Suh, Zhenghong Jiang, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Behavior-level observability don't-cares and application to low-power behavioral synthesis

Jason Cong, Zhiru Zhang, Bin Liu, 2009, ISLPED.

xPilot: A Platform-Based Behavioral Synthesis System

Jason Cong, Zhiru Zhang, Deming Chen, 2005 .

PRIMAL: Power Inference using Machine Learning

Yuan Zhou, Zhiru Zhang, Brucek Khailany, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Instruction set extension with shadow registers for configurable processors

Jason Cong, Zhiru Zhang, Glenn Reinman, 2005, FPGA '05.

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Jason Cong, Cody Hao Yu, Zhe Chen, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Zhiru Zhang, Bin Liu, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Painting on PIacement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets

Zhiru Zhang, Cunxi Yu, Cunxi Yu, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations

Nitish Srivastava, Hongbo Rong, Zhiru Zhang, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations pdf

Zhiru Zhang, G. Edward Suh, Ritchie Zhao, 2020, ICLR.

Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators pdf

Zhiru Zhang, Christopher De Sa, Ritchie Zhao, 2019, ArXiv.

Statistically certified approximate logic synthesis

Zhiru Zhang, Gai Liu, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Christopher Torng, Khalid Al-Hawaj, Christopher Batten, 2019, 2019 Symposium on VLSI Circuits.

Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors

Jason Cong, Zhiru Zhang, Guoling Han, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Image classification with spectral and texture features based on SVM

Zhiru Zhang, Fen Chen, Dongmei Yan, 2010, 2010 18th International Conference on Geoinformatics.

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Christopher Torng, Christopher Batten, Ronald G. Dreslinski, 2018, IEEE Micro.

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ICCAD 2003.

Reverse engineering convolutional neural networks through side-channel information leaks

Zhiru Zhang, G. Edward Suh, Weizhe Hua, 2018, DAC 2018.

Channel Gating Neural Networks

Zhiru Zhang, Christopher De Sa, G. Edward Suh, 2018, NeurIPS.

Scheduling with integer time budgeting for low-power optimization

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Jason Cong, Cody Hao Yu, Zhe Chen, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

A New Approach to Automatic Memory Banking using Trace-Based Address Mining

Zhiru Zhang, Yuan Zhou, Khalid Musa Al-Hawaj, 2017, FPGA.

LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure

Zhiru Zhang, Cunxi Yu, Shaojie Xiang, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Improving Neural Network Quantization using Outlier Channel Splitting

Zhiru Zhang, Christopher De Sa, Yuwei Hu, 2019 .

GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning pdf

Zhiru Zhang, G. Edward Suh, Weizhe Hua, 2020, ArXiv.

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis

Zhiru Zhang, Rajit Manohar, Steve Dai, 2017, FPGA.

Session details: Designer's Day Session 2

Zhiru Zhang, 2015, FPGA 2015.

Gradual Relaxation Techniques with Applications to Behavioral Synthesis

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2003, ICCAD.

FeatGraph: A Flexible and Efficient Backend for Graph Neural Network Systems pdf

Zhiru Zhang, Zheng Zhang, Jiali Yu, 2020, ArXiv.

AutoPilot: A Platform-Based ESL Synthesis System

Jason Cong, Zhiru Zhang, Yiping Fan, 2008 .

Platform-Based Behavior-Level and System-Level Synthesis

Jason Cong, Zhiru Zhang, Wei Jiang, 2006, 2006 IEEE International SOC Conference.

Rapid Generation of High-Quality RISC-V Processors from Functional Instruction Set Specifications

Zhiru Zhang, Gai Liu, Joseph Primmer, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

SDC-based modulo scheduling for pipeline synthesis

Zhiru Zhang, Bin Liu, B. Liu, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Improving high-level synthesis with decoupled data structure optimization

Shreesha Srinath, Christopher Batten, Zhiru Zhang, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Jason Cong, Zhiru Zhang, Deming Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

Accelerating Neural Networks using Channel Gating

Zhiru Zhang, Christopher De Sa, G. Edward Suh, 2018, MICRO 2018.

Architecture and synthesis for on-chip multicycle communication

Jason Cong, Zhiru Zhang, Xun Yang, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enabling adaptive loop pipelining in high-level synthesis

Zhiru Zhang, Gai Liu, Ritchie Zhao, 2017, 2017 51st Asilomar Conference on Signals, Systems, and Computers.

MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration pdf

Zhiru Zhang, G. Edward Suh, Muhammad Umar, 2020, ArXiv.

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration

Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, 2017, 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW).

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks

Zhiru Zhang, Zhijing Li, Debjit Pal, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing

Jason Cong, Cody Hao Yu, Yuan Zhou, 2019, FPGA.

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ICCAD.

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning

Evangeline F. Y. Young, Yuan Zhou, Zhiru Zhang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis

Jason Cong, Zhiru Zhang, Bin Liu, 2010, TODE.

Flushing-enabled loop pipelining for high-level synthesis

Zhiru Zhang, Kecheng Hao, Mingxing Tan, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Scheduling with soft constraints

Jason Cong, Zhiru Zhang, Bin Liu, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets

Zhiru Zhang, Cunxi Yu, 2019 .

Architectural Specialization for Inter-Iteration Loop Dependence Patterns

Shreesha Srinath, Berkin Ilbeyi, Christopher Batten, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

Yuan Zhou, Zhiru Zhang, Wenping Wang, 2018, FPGA.

GraphZoom: A multi-level spectral approach for accurate and scalable graph embedding pdf

Zhiru Zhang, Zhiqiang Zhao, Chenhui Deng, 2020, ICLR.

Reverse Engineering Convolutional Neural Networks Through Side-channel Information Leaks

Zhiru Zhang, G. Edward Suh, Weizhe Hua, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

High-level Synthesis for Low-power Design

Zhiru Zhang, Deming Chen, Keith A. Campbell, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

Revisiting bitwidth optimizations

Jason Cong, Zhiru Zhang, Bin Liu, 2009, FPGA '09.

A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping

Zhiru Zhang, Gai Liu, 2017, FPGA.

Multithreaded pipeline synthesis for data-parallel kernels

Zhiru Zhang, Bin Liu, Mingxing Tan, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Architecture and synthesis for multi-cycle on-chip communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

Architecture and compilation for data bandwidth improvement in configurable embedded processors

Jason Cong, Zhiru Zhang, Guoling Han, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Architecture-level synthesis for automatic interconnect pipelining

Jason Cong, Zhiru Zhang, Yiping Fan, 2004, Proceedings. 41st Design Automation Conference, 2004..

FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations pdf

Zhiru Zhang, Deming Chen, Yichi Zhang, 2020, FPGA.

Architecture and synthesis for multi-cycle communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ISPD '03.

Behavior andCommunication Co-Optimization forSystems withSequential Communication Media

Zhiru Zhang, Guoling Han, 2006 .

Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs

Christina Delimitrou, Zhiru Zhang, Shaojie Xiang, 2020, IEEE Computer Architecture Letters.

Building Efficient Deep Neural Networks With Unitary Group Convolutions

Zhiru Zhang, Christopher De Sa, Yuwei Hu, 2018, 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider

Zhiru Zhang, Robert Stone, Louise Skinnari, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

Rajesh Gupta, Zhiru Zhang, Mani B. Srivastava, 2017, FPGA.

Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES

Zhiru Zhang, G. Edward Suh, Zhenghong Jiang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning

Zhiru Zhang, Steve Dai, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

Jason Cong, Zhiru Zhang, Shih-Chieh Chang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Bitwidth-aware scheduling and binding in high-level synthesis

Zhiru Zhang, Yiping Fan, Xu Cheng, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Bitwidth-aware scheduling and binding in high-level synthesis

Jason Cong, Zhiru Zhang, Xu Cheng, 2005, ASP-DAC.

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Jason Cong, Zhiru Zhang, Deming Chen, 2016, IET Cyper-Phys. Syst.: Theory & Appl..

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation

Zhiru Zhang, Gai Liu, Steve Dai, 2018, FPGA.