Andrea Biagioni

Giulia De Bonis, Pier Stanislao Paolucci, Roberto Ammendola, 2018, 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture pdf

Pier Stanislao Paolucci, Davide Rossetti, Andrea Biagioni, 2012, ArXiv.

NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

Davide Rossetti, Roberto Ammendola, Andrea Biagioni, 2014 .

GPU Peer-to-Peer Techniques Applied to a Cluster Interconnect

Massimo Bernaschi, Mauro Bisson, Massimiliano Fatica, 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

A 34 Gbps data transmission system with FPGAs embedded transceivers and QSFP+ modules

Davide Rossetti, Roberto Ammendola, Andrea Biagioni, 2012, 2012 IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC).

NaNet: a Reconfigurable PCIe Network Interface Card Architecture for Real-time Distributed Heterogeneous Stream Processing in the NA62 Low Level Trigger.

Giulia De Bonis, Andrea Biagioni, Francesca Lo Cicero, 2019 .

A hierarchical watchdog mechanism for systemic fault awareness on distributed systems

Pier Stanislao Paolucci, Davide Rossetti, Roberto Ammendola, 2015, Future Gener. Comput. Syst..

APEnet+: a 3D Torus network optimized for GPU-based HPC Systems

Davide Rossetti, Roberto Ammendola, Andrea Biagioni, 2012 .

Graphics Processors in HEP Low-Level Trigger Systems

Davide Rossetti, Andrea Biagioni, Gianluca Lamanna, 2016 .

Power-Efficient Computing: Experiences from the COSA Project

Pier Stanislao Paolucci, Enrico Calore, Sebastiano Fabio Schifano, 2017, Sci. Program..

EuroEXA Custom Switch: an innovative FPGA-based system for extreme scale computing in Europe

Andrea Biagioni, Francesca Lo Cicero, Luca Pontisso, 2020 .

QUonG: A GPU-based HPC System Dedicated to LQCD Computing

Davide Rossetti, Roberto Ammendola, Andrea Biagioni, 2011, 2011 Symposium on Application Accelerators in High-Performance Computing.

The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems

Y. Zhang, Martin L. Kersten, Nikolaos D. Kallimanis, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores pdf

Pier Stanislao Paolucci, Roberto Ammendola, Andrea Biagioni, 2015, ArXiv.

Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems pdf

Pier Stanislao Paolucci, Davide Rossetti, Roberto Ammendola, 2013, ArXiv.

NaNet-10: a 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector.

Davide Rossetti, Andrea Biagioni, Michele Martinelli, 2016 .

Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface

Pier Stanislao Paolucci, Davide Rossetti, Roberto Ammendola, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Development of Network Interface Cards for TRIDAQ systems with the NaNet framework

Paolo Valente, Davide Rossetti, Andrea Biagioni, 2017 .

UvA-DARE (Digital Academic Repository) Event reconstruction for KM3NeT/ORCA using convolutional neural networks

Francesco Leone, Mancia Anguita, Riccardo Papaleo, 2020 .

GPU-based low-level trigger system for the standalone reconstruction of the ring-shaped hit patterns in the RICH Cherenkov detector of NA62 experiment

Davide Rossetti, M. Piccini, Andrea Biagioni, 2017 .

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities

Pier Stanislao Paolucci, Davide Rossetti, Roberto Ammendola, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report pdf

Pier Stanislao Paolucci, Gert Goossens, Davide Rossetti, 2013, ArXiv.

LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System

Pier Stanislao Paolucci, Davide Rossetti, Roberto Ammendola, 2014, 2014 IEEE 33rd International Symposium on Reliable Distributed Systems.

Gaussian and Exponential Lateral Connectivity on Distributed Spiking Neural Network Simulation

Giulia De Bonis, Pier Stanislao Paolucci, Roberto Ammendola, 2018, 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).

NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features pdf

Maurizio Martinelli, Pier Stanislao Paolucci, Davide Rossetti, 2014, ArXiv.

Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses pdf

Pier Stanislao Paolucci, Roberto Ammendola, Andrea Biagioni, 2015, ArXiv.

APEnet+ 34 Gbps data transmission system and custom transmission logic

Davide Rossetti, Roberto Ammendola, Andrea Biagioni, 2013 .

NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing

Davide Rossetti, Roberto Ammendola, Andrea Biagioni, 2015 .

TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale

Massimo Bernaschi, Giovanni Agosta, Bérenger Bramas, 2021, 2021 24th Euromicro Conference on Digital System Design (DSD).

Architecture and performance of the KM3NeT front-end firmware

Francesco Leone, Joern Wilms, Mancia Anguita, 2021, Journal of Astronomical Telescopes, Instruments, and Systems.