Somnath Paul

发表

Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection

Gert Cauwenberghs, Sadique Sheik, Somnath Paul, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks

Swarup Bhunia, Somnath Paul, Jongsun Park, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A circuit-software co-design approach for improving EDP in reconfigurable frameworks

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS

Hong Wang, Deepak Mathaikutty, Sriram R. Vangal, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Challenges in Computing for Nanoscale Technologies

Swarup Bhunia, Somnath Paul, 2014 .

Collective computing based on swarm intelligence

Swarup Bhunia, Somnath Paul, Seetharam Narasimhan, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Low-overhead design technique for calibration of maximum frequency at multiple operating points

Swarup Bhunia, Hamid Mahmoodi, Somnath Paul, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Reconfigurable computing using content addressable memory for improved performance and resource usage

Swarup Bhunia, Somnath Paul, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Design Space Exploration for MBC Based Generic Reconfigurable Computing Framework

Swarup Bhunia, Somnath Paul, 2014 .

An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications

Swarup Bhunia, Somnath Paul, Robert Karam, 2016, IEEE Transactions on Computers.

Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement

Swarup Bhunia, Somnath Paul, S. Bhunia, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On distance and distance Laplacian spectra of corona of two graphs

Somnath Paul, Somnath Paul, 2016, Discret. Math. Algorithms Appl..

Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications

Swarup Bhunia, Somnath Paul, Ruchir Puri, 2017, ACM J. Emerg. Technol. Comput. Syst..

Memory based computation using embedded cache for processor yield and reliability improvement

Swarup Bhunia, Somnath Paul, 2007, 2007 25th International Conference on Computer Design.

Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting

Gert Cauwenberghs, Sadique Sheik, Somnath Paul, 2018, 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Pre-synaptic learning using delayed causal updates

Somnath Paul, Charles Augustine, Muhammad M. Khellah, 2017 .

Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory

Lei Wang, Swarup Bhunia, Somnath Paul, 2012, 2012 25th International Conference on VLSI Design.

Key Features of Memory-Based Computing

Swarup Bhunia, Somnath Paul, 2014 .

Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks

Swarup Bhunia, Somnath Paul, Anandaroop Ghosh, 2012, 2012 25th International Conference on VLSI Design.

Robust low-power reconfigurable computing with a variation-aware preferential design approach

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2014, 2014 IEEE International Conference on IC Design & Technology.

Motivation for a Memory-Based Computing Hardware

Swarup Bhunia, Somnath Paul, 2014 .

Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration

Swarup Bhunia, Somnath Paul, Sivasubramaniam Krishnamurthy, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection

Swarup Bhunia, Hamid Mahmoodi, Somnath Paul, 2010, TODE.

On the distance signless Laplacian spectral radius and the distance signless Laplacian energy of graphs

Somnath Paul, Abdollah Alhevaz, Maryam Baghipur, 2018, Discret. Math. Algorithms Appl..

Compute-in-Memory Architecture for Data-Intensive Kernels

Swarup Bhunia, Somnath Paul, Robert Karam, 2017 .

A Memory Based Generic Reconfigurable Framework

Swarup Bhunia, Somnath Paul, 2014 .

Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache

Swarup Bhunia, Xinmiao Zhang, Somnath Paul, 2011, IEEE Transactions on Computers.

Application Mapping to MBC Hardware

Swarup Bhunia, Somnath Paul, 2014 .

Synaptic sampling in hardware spiking neural networks

Gert Cauwenberghs, Sadique Sheik, Somnath Paul, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

On the Minimal Distance spectral radius in the Class of bicyclic graphs

Somnath Paul, Milan Nath, 2014, Discret. Math. Algorithms Appl..

Forward table-based presynaptic event-triggered spike-timing-dependent plasticity

Gert Cauwenberghs, Siddharth Joshi, Sadique Sheik, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

VAIL: Variation-aware issue logic and performance binning for processor yield and profit improvement

Swarup Bhunia, Somnath Paul, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Energy-efficient hardware acceleration through computing in the memory

Swarup Bhunia, Somnath Paul, Ruchir Puri, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications

Swarup Bhunia, Somnath Paul, Robert Karam, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Off-Chip MAHA Using NAND Flash Technology

Swarup Bhunia, Somnath Paul, 2014 .

Computing with nanoscale memory: Model and architecture

Swarup Bhunia, Somnath Paul, S. Bhunia, 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

Memory-Efficient Synaptic Connectivity for Spike-Timing- Dependent Plasticity

Siddharth Joshi, Gert Cauwenberghs, Sadique Sheik, 2019, Front. Neurosci..

Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach

Kaushik Roy, Christos A. Papachristou, Francis G. Wolff, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Conjugate Laplacian matrices of a graph

Somnath Paul, 2018, Discret. Math. Algorithms Appl..

On-demand transparency for improving hardware Trojan detectability

Swarup Bhunia, Rajat Subhra Chakraborty, Somnath Paul, 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips

Swarup Bhunia, Rajat Subhra Chakraborty, Somnath Paul, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware

Swarup Bhunia, Somnath Paul, Robert Karam, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Mitigating the Effect of Parametric Failures in MBC Frameworks

Swarup Bhunia, Somnath Paul, 2014 .

The spectra of a new join of graphs

Somnath Paul, Somnath Paul, 2018, Discret. Math. Algorithms Appl..

Reliability improvement in multicore architectures through computing in embedded memory

Swarup Bhunia, Somnath Paul, Prabhat Mishra, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A note on the Distance spectral radius of some graphs

Somnath Paul, Milan Nath, 2014, Discret. Math. Algorithms Appl..

Exploring Spin Transfer Torque Devices for Unconventional Computing

Kaushik Roy, Mrigank Sharad, Xuanyao Fong, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Nanoscale reconfigurable computing using non-volatile 2-D STTRAM array

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)

Swarup Bhunia, Somnath Paul, 2011, FPGA '11.

Application of Memory-Based Computing

Swarup Bhunia, Somnath Paul, 2014 .

Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect

Yu Zhou, Swarup Bhunia, Somnath Paul, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Mitigating the Effect of Runtime-Failures in MBC Frameworks

Swarup Bhunia, Somnath Paul, 2014 .

An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design

Somnath Paul, Soumya Pandit, Abhijit Dana, 2013, VDAT.

Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2008, ICCAD 2008.

Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping

Yu Zhou, Swarup Bhunia, Rajat Subhra Chakraborty, 2009, IET Comput. Digit. Tech..

Computing with Memory for Energy-Efficient Robust Systems

Swarup Bhunia, Somnath Paul, 2013 .

Preferential Memory Design for MBC Frameworks

Swarup Bhunia, Somnath Paul, 2014 .

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis

Kaushik Roy, Christos A. Papachristou, Francis G. Wolff, 2013, IEEE Transactions on Computers.

Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines

Somnath Paul, Charles Augustine, Emre Neftci, 2016, Front. Neurosci..

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning

Gert Cauwenberghs, Nikil D. Dutt, Jeffrey L. Krichmar, 2017, Front. Neurosci..

On the sum of the distance signless Laplacian eigenvalues of a graph and some inequalities involving them

Somnath Paul, Abdollah Alhevaz, Maryam Baghipur, 2020, Discret. Math. Algorithms Appl..

Adaptive ECC for Tailored Protection of Nanoscale Memory

Swarup Bhunia, Somnath Paul, Jongsun Park, 2017, IEEE Design & Test.

Hardware/software co-design of a high-end mixed signal microcontroller

Somnath Paul, Rajat Gupta, S. Venkataraman, 1998, Proceedings Eleventh International Conference on VLSI Design.

MERO: A Statistical Approach for Hardware Trojan Detection

Christos A. Papachristou, Francis G. Wolff, Swarup Bhunia, 2009, CHES.

On the Maximal Distance spectral radius in a Class of bicyclic Graphs

Somnath Paul, 2012, Discret. Math. Algorithms Appl..

System level self-healing for parametric yield and reliability improvement under power bound

Christos A. Papachristou, Francis G. Wolff, Swarup Bhunia, 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing

Swarup Bhunia, Somnath Paul, Xinmu Wang, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield

Swarup Bhunia, Rajat Subhra Chakraborty, Somnath Paul, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Event-driven random backpropagation: Enabling neuromorphic deep learning machines

Somnath Paul, Charles Augustine, Emre Neftci, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

PLA Based Application Mapping in MBC

Swarup Bhunia, Somnath Paul, 2014 .

Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement

Yu Zhou, Swarup Bhunia, Somnath Paul, 2008, 2008 Design, Automation and Test in Europe.

Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach

Swarup Bhunia, Somnath Paul, Saibal Mukhopadhyay, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices

Swarup Bhunia, Somnath Paul, S. Bhunia, 2008, 2008 Asia and South Pacific Design Automation Conference.

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

Amit Agarwal, Steven Hsu, Ram Krishnamurthy, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.