Sanjay B. Patel

Efficient compression of deterministic patterns into multiple PRPG seeds

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2005, IEEE International Conference on Test, 2005..

Hierarchical compactor design for diagnosis in deterministic logic BIST

Peter Wohl, John A. Waicukauski, Sanjay Patel, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Scalable selector architecture for X-tolerant deterministic BIST

Peter Wohl, John A. Waicukauski, Sanjay Patel, 2004, Proceedings. 41st Design Automation Conference, 2004..

X-tolerant compression and application of scan-atpg patterns in a bist architecture

Minesh B. Amin, Peter Wohl, John A. Waicukauski, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Efficient compression and application of deterministic patterns in a logic BIST architecture

Minesh B. Amin, Peter Wohl, John A. Waicukauski, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Effective diagnostics through interval unloads in a BIST environment

Gregory A. Maston, J. Waicukauski, P. Wohl, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).