FeiFei Zhao

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains

Nur A. Touba, Fangfang Li, Wen-Ben Jone, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Logic BIST Architecture for System-Level Test and Diagnosis

Shianling Wu, Yuan Zuo, Xingang Wang, 2009, 2009 Asian Test Symposium.