Vikram Iyengar

发表

Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking

Érika F. Cota, Chunsheng Liu, Vikram Iyengar, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

David E. Lackey, Vikram Iyengar, Kenneth Pichamuthu, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

An Efficient Finite-State Machine Implementation of Huffman Decoders

Krishnendu Chakrabarty, Vikram Iyengar, 1997, Inf. Process. Lett..

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters

Krishnendu Chakrabarty, Vikram Iyengar, Brian T. Murray, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Efficient test access mechanism optimization for system-on-chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A unified approach for SoC testing using test data compression and TAM optimization

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Test Scheduling Using Mixed-Integer Linear Programming

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking

Chunsheng Liu, Vikram Iyengar, 2006, Proceedings of the Design Automation & Test in Europe Conference.

At-Speed Structural Test For High-Performance ASICs

Mark Johnson, Vikram Iyengar, Frank Woytowich, 2006, 2006 IEEE International Test Conference.

Performance verification of high-performance ASICs using at-speed structural test

Mark Johnson, Vikram Iyengar, Frank Woytowich, 2006, GLSVLSI '06.

A set of benchmarks for modular testing of SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings. International Test Conference.

Physically-Aware N-Detect Test

Peter Lloyd, Vikram Iyengar, Yen-Tzu Lin, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors

Elizabeth M. Rudnick, Vikram Iyengar, Ta-Chung Chang, 2000, J. Electron. Test..

A flexible and scalable methodology for GHz-speed structural test

Vikram Iyengar, Gary Grise, Mark Taylor, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Design and optimization of multi-level TAM architectures for hierarchical SOCs

Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Microprocessor Design Verification

Elizabeth M. Rudnick, Vikram Iyengar, E. Rudnick, 2000, The VLSI Handbook.

Efficient Wrapper/TAM co-optimization for large SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Till death do us part : five stories

Vikram Iyengar, Mahāśvetā Debī, 2001 .

Test Resource Partitioning for System-on-a-Chip

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002, Frontiers in electronic testing.

Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip

Krishnendu Chakrabarty, Vikram Iyengar, K. Chakrabarty, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

On the use of k-tuples for SoC test schedule representation

Sandeep Koranne, Vikram Iyengar, S. Koranne, 2002, Proceedings. International Test Conference.

A unified SOC test approach based on test data compression and TAM design

Vikram Iyengar, Anshuman Chandra, A. Chandra, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

M1078 Hybrid Hydraulic Vehicle Fuel Economy Evaluation

Jack Harris, Vikram Iyengar, Walter Olson, 2012 .

Test planning for modular testing of hierarchical SOCs

Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Recent advances in test planning for modular testing of core-based SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints

Krishnendu Chakrabarty, Vikram Iyengar, Sandeep Kumar Goel, 2002, Proceedings. International Test Conference.

Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

Mark Johnson, Vikram Iyengar, Frank Woytowich, 2006, IEEE Custom Integrated Circuits Conference 2006.

Built-in self testing of sequential circuits using precomputed test sets

Krishnendu Chakrabarty, Vikram Iyengar, Brian T. Murray, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Deterministic Built-in Pattern Generation for Sequential Circuits

Krishnendu Chakrabarty, Vikram Iyengar, Brian T. Murray, 1999, J. Electron. Test..

Test Resource Partitioning

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores

Makoto Sugihara, Vikram Iyengar, Krishnendu Chakrabarty, 2001 .

User interfaces for continuum robot arms

Ian D. Walker, Vikram Iyengar, Matthew A. Csencsits, 2005, 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems.

Huffman encoding of test sets for sequential circuits

Krishnendu Chakrabarty, Vikram Iyengar, Brian T. Murray, 1998, IEEE Trans. Instrum. Meas..

Could Kill Switches Kill Phone Theft? Surveying Potential Solution for Smartphone Theft

Vikram Iyengar, Matt Reitfors, 2016 .

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints

Krishnendu Chakrabarty, Vikram Iyengar, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test Bus Sizing for System-on-a-Chip

Krishnendu Chakrabarty, Vikram Iyengar, 2002, IEEE Trans. Computers.

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Krishnendu Chakrabarty, Sule Ozev, Vikram Iyengar, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Precedence-Based, Preemptive, and Power-Constrained Test Scheduling

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Frequency-Directed Run-Length (FDR) Codes

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Test Access Mechanism Optimization

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Test Wrapper and TAM Co-Optimization

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Variation-aware performance verification using at-speed structural test and statistical timing

Jinjun Xiong, David E. Lackey, Vladimir Zolotov, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Improved Test Bus Partitioning

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, J. Electron. Test..

Test Data Compression Using Golomb Codes

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Thermal-aware testing of network-on-chip using multiple-frequency clocking

Dhiraj K. Pradhan, Chunsheng Liu, Vikram Iyengar, 2006, 24th IEEE VLSI Test Symposium.

Low cost at-speed testing using On-Product Clock Generation compatible with test compression

Vivek Chickermane, Brian Foutz, Brion L. Keller, 2010, 2010 IEEE International Test Conference.

Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores

Krishnendu Chakrabarty, Makoto Sugihara, Vikram Iyengar, 2000, PDPTA.

SOC Test Planning Using Virtual Test

Krishnendu Chakrabarty, Vikram Iyengar, Anuja Sehgal, 2004 .

On using rectangle packing for SOC wrapper/TAM co-optimization

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Test cost reduction for SOCs using TAMs and Lagrange multipliers

Krishnendu Chakrabarty, Vikram Iyengar, Anuja Sehgal, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs

Krishnendu Chakrabarty, Sule Ozev, Vikram Iyengar, 2007, 2007 Asia and South Pacific Design Automation Conference.

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon

Vikram Iyengar, Peter Lloyd, Yen-Tzu Lin, 2008, 2008 IEEE International Test Conference.

Variation-aware performance verification using at-speed structural test and statistical timing

Jinjun Xiong, David E. Lackey, Vladimir Zolotov, 2007, ICCAD 2007.

SOC test planning using virtual test access architectures

Krishnendu Chakrabarty, Vikram Iyengar, Anuja Sehgal, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Test set encoding for efficient sequential circuit testing

Krishnendu Chakrabarty, Vikram Iyengar, B. T. Murray, 1997, IEEE Instrumentation and Measurement Technology Conference Sensing, Processing, Networking. IMTC Proceedings.

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2003, IEEE Trans. Computers.

TRP for Low-Power Scan Testing

Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra, 2002 .

Built-in test pattern generation for high-performance circuits using twisted-ring counters

Krishnendu Chakrabarty, Vikram Iyengar, Brian T. Murray, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Thermal-aware test scheduling and hot spot temperature minimization for core-based systems

Chunsheng Liu, Vikram Iyengar, Kugesh Veeraraghavant, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs

Erik Jan Marinissen, Krishnendu Chakrabarty, Vikram Iyengar, 2002, DAC '02.

Statistical Test To Uncover Process Variations

Jinjun Xiong, Vladimir Zolotov, Vikram Iyengar, 2008 .

Real Time Implementation of DOC-DPF Models on a Production-Intent ECU for Controls and Diagnostics of a PM Emission Control System

Vikram Iyengar, Arkadiusz Kalinowski, Xiaolai He, 2009 .