Michael A. Kochte

发表

A novel scan segmentation design method for avoiding shift timing failure in scan testing

Xiaoqing Wen, Kohei Miyase, Yuta Yamato, 2011, 2011 IEEE International Test Conference.

Autonomous Testing for 3D-ICs with IEEE Std. 1687

Kuen-Jong Lee, Hans-Joachim Wunderlich, Michael A. Kochte, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

On Determining the Real Output Xs by SAT-Based Reasoning

Hans-Joachim Wunderlich, Michael A. Kochte, Melanie Elm, 2010, 2010 19th IEEE Asian Test Symposium.

Accurate QBF-based test pattern generation in presence of unknown values

Bernd Becker, Matthias Sauer, Hans-Joachim Wunderlich, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power-aware test generation with guaranteed launch safety for at-speed scan testing

Mark Mohammad Tehranipoor, Xiaoqing Wen, Patrick Girard, 2011, 29th VLSI Test Symposium.

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns

Bernd Becker, Matthias Sauer, Hans-Joachim Wunderlich, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Boolean reasoning for digital circuits in presence of unknown values: application to test automation

Michael A. Kochte, M. Kochte, 2014 .

Specification and verification of security in reconfigurable scan networks

Pascal Raiola, Bernd Becker, Matthias Sauer, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Norbert Wehn, Mehdi Baradaran Tahoori, Michael Glaß, 2014, Microelectron. Reliab..

Built-In Test for Hidden Delay Faults

Chang Liu, Hans-Joachim Wunderlich, Sybille Hellebrand, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient observation point selection for aging monitoring

Chang Liu, Hans-Joachim Wunderlich, Michael A. Kochte, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Formal verification of secure reconfigurable scan network infrastructure

Bernd Becker, Matthias Sauer, Hans-Joachim Wunderlich, 2016, 2016 21th IEEE European Test Symposium (ETS).

GPU-accelerated small delay fault simulation

Xiaoqing Wen, Hans-Joachim Wunderlich, Michael A. Kochte, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects

Chang Liu, Hans-Joachim Wunderlich, Sybille Hellebrand, 2014, 2014 International Test Conference.

Test pattern generation in presence of unknown values based on restricted symbolic logic

Bernd Becker, Matthias Sauer, Hans-Joachim Wunderlich, 2014, 2014 International Test Conference.

Securing Access to Reconfigurable Scan Networks

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2013, 2013 22nd Asian Test Symposium.

Accurate X-Propagation for Test Applications by SAT-Based Reasoning

Hans-Joachim Wunderlich, Michael A. Kochte, Melanie Elm, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An on-chip self-test architecture with test patterns recorded in scan chains

Kuen-Jong Lee, Michael A. Kochte, Pin-Hao Tang, 2016, 2016 IEEE International Test Conference (ITC).

A framework for scheduling parallel dbms user-defined programs on an attached high-performance computer

Ramesh Natarajan, Michael A. Kochte, 2008, CF '08.

Efficient BDD-based Fault Simulation in Presence of Unknown Values

Xiaoqing Wen, Kohei Miyase, Sandip Kundu, 2011, 2011 Asian Test Symposium.

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch

Xiaoqing Wen, Kohei Miyase, Hans-Joachim Wunderlich, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

GUARD: GUAranteed reliability in dynamically reconfigurable systems

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Test Strategies for Reliable Runtime Reconfigurable Architectures

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2013, IEEE Transactions on Computers.

Cross- Layer Dependability Modeling and Abstraction in Systems on Chip

Norbert Wehn, Michael Glaß, Jürgen Teich, 2013 .

Analysis and mitigation or IR-Drop induced scan shift-errors

Xiaoqing Wen, Kohei Miyase, Hans-Joachim Wunderlich, 2017, 2017 IEEE International Test Conference (ITC).

Adaptive multi-layer techniques for increased system dependability

Wolfgang Rosenstiel, Jörg Henkel, Hongyan Zhang, 2015, it Inf. Technol..

Optimized Selection of Frequencies for Faster-Than-at-Speed Test

Hans-Joachim Wunderlich, Sybille Hellebrand, Michael A. Kochte, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

Paolo Prinetto, Stefano Di Carlo, Hans-Joachim Wunderlich, 2010, 2010 19th IEEE Asian Test Symposium.

Efficient multi-level fault simulation of HW/SW systems for structural faults

Paolo Prinetto, Stefano Di Carlo, Hans-Joachim Wunderlich, 2011, Science China Information Sciences.

System reliability evaluation using concurrent multi-level simulation of structural faults

Paolo Prinetto, Stefano Di Carlo, Hans-Joachim Wunderlich, 2010, 2010 IEEE International Test Conference.

Structure-Oriented Test of Reconfigurable Scan Networks

Hans-Joachim Wunderlich, Michael A. Kochte, Dominik Ull, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Dependable on-chip infrastructure for dependable MPSOCs

Hans-Joachim Wunderlich, Michael A. Kochte, 2016, 2016 17th Latin-American Test Symposium (LATS).

LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing

Xiaoqing Wen, Kohei Miyase, Yuta Yamato, 2013, IEEE Design & Test.

Aging monitor reuse for small delay fault testing

Chang Liu, Hans-Joachim Wunderlich, Michael A. Kochte, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Modeling, verification and pattern generation for reconfigurable scan networks

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2012, 2012 IEEE International Test Conference.

Multi-level timing simulation on GPUs

Hans-Joachim Wunderlich, Michael A. Kochte, Eric Schneider, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test

Xiaoqing Wen, Hans-Joachim Wunderlich, Yuta Yamato, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

SAT-based code synthesis for fault-secure circuits

Hans-Joachim Wunderlich, Michael A. Kochte, Atefe Dalirsani, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2013, 2013 IEEE International Test Conference (ITC).

Exact stuck-at fault classification in presence of unknowns

Bernd Becker, Hans-Joachim Wunderlich, Michael A. Kochte, 2012, 2012 17th IEEE European Test Symposium (ETS).

Synthesis of Fault-Tolerant Reconfigurable Scan Networks

Hans-Joachim Wunderlich, Michael A. Kochte, Sebastian Brandhofer, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Low-overhead fault-tolerance for the preconditioned conjugate gradient solver

Claus Braun, Hans-Joachim Wunderlich, Michael A. Kochte, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures

Jorg Henkel, Hongyan Zhang, Hans-Joachim Wunderlich, 2021 .

Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead

Hans-Joachim Wunderlich, Michael A. Kochte, Christian G. Zoellin, 2009, 2009 14th IEEE European Test Symposium.

Trustworthy reconfigurable access to on-chip infrastructure

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2017, 2017 International Test Conference in Asia (ITC-Asia).

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Xiaoqing Wen, Kohei Miyase, Hans-Joachim Wunderlich, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2017, IEEE Transactions on Computers.

Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations

Claus Braun, Hans-Joachim Wunderlich, Michael A. Kochte, 2016, 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

Transparent structural online test for reconfigurable systems

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

Self-Test and Diagnosis for Self-Aware Systems

Hans-Joachim Wunderlich, Michael A. Kochte, 2018, IEEE Design & Test.

Test Strategies for Reconfigurable Scan Networks

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Area-efficient synthesis of fault-secure NoC switches

Hans-Joachim Wunderlich, Michael A. Kochte, Atefe Dalirsani, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Kuen-Jong Lee, Michael A. Kochte, Wen-Hsuan Hsu, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Test Encoding for Extreme Response Compaction

Hans-Joachim Wunderlich, Michael A. Kochte, Stefan Holst, 2009, 2009 14th IEEE European Test Symposium.

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures

Cecilia Metra, Martin Omaña, Hans-Joachim Wunderlich, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2015, TODE.

Efficient Concurrent Self-Test with Partially Specified Patterns

Hans-Joachim Wunderlich, Michael A. Kochte, Christian G. Zoellin, 2010, J. Electron. Test..

SAT-based fault coverage evaluation in the presence of unknown values

Hans-Joachim Wunderlich, Michael A. Kochte, 2011, 2011 Design, Automation & Test in Europe.

Fine-Grained Access Management in Reconfigurable Scan Networks

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accurate Multi-cycle ATPG in Presence of X-Values

Bernd Becker, Matthias Sauer, Hans-Joachim Wunderlich, 2013, 2013 22nd Asian Test Symposium.

Advances in hardware reliability of reconfigurable many-core embedded systems

Jorg Henkel, Hongyan Zhang, Hans-Joachim Wunderlich, 2019 .

Scan pattern retargeting and merging with reduced access time

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2013, 2013 18th IEEE European Test Symposium (ETS).

Verifikation Rekonfigurierbarer Scan-Netze

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2014, MBMV.

Online prevention of security violations in reconfigurable scan networks

Pascal Raiola, Bernd Becker, Matthias Sauer, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Packet-Switching Networks on Systems-on-a-Chip

Michael A. Kochte, 2003 .

Exact Logic and Fault Simulation in Presence of Unknowns

Bernd Becker, Matthias Sauer, Hans-Joachim Wunderlich, 2014, TODE.

Detecting and Resolving Security Violations in Reconfigurable Scan Networks

Pascal Raiola, Bernd Becker, Matthias Sauer, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Efficient on-line fault-tolerance for the preconditioned conjugate gradient method

Claus Braun, Hans-Joachim Wunderlich, Michael A. Kochte, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

OTERA: Online test strategies for reliable reconfigurable architectures — Invited paper for the AHS-2012 special session “Dependability by reconfigurable hardware”

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

Test exploration and validation using transaction level models

Paolo Prinetto, Stefano Di Carlo, Martin Radetzki, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Test Set Stripping Limiting the Maximum Number of Specified Bits

Hans-Joachim Wunderlich, Michael A. Kochte, Michael E. Imhof, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

GPU-Accelerated Simulation of Small Delay Faults

Xiaoqing Wen, Hans-Joachim Wunderlich, Michael A. Kochte, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accurate QBF-based test pattern generation in presence of unknown values

Bernd Becker, Hans-Joachim Wunderlich, Michael A. Kochte, 2013, DATE 2013.

STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures

Jörg Henkel, Hongyan Zhang, Lars Bauer, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses

Hans-Joachim Wunderlich, Michael A. Kochte, Stefan Holst, 2019, 2019 IEEE International Test Conference (ITC).

Access Port Protection for Reconfigurable Scan Networks

Hans-Joachim Wunderlich, Michael A. Kochte, Rafal Baranowski, 2014, Journal of Electronic Testing.

Efficient fault simulation on many-core processors

Hans-Joachim Wunderlich, Michael A. Kochte, Christian G. Zoellin, 2010, Design Automation Conference.

Imaging planets about other stars with UMBRAS: target acquisition and station keeping

Michael A. Kochte, Dorothy A. Fraquelli, Alfred B. Schultz, 2000 .

Preprint Optimized Selection of Frequencies for Faster-Thanat-Speed Test

Hans-Joachim Wunderlich, Sybille Hellebrand, Michael A. Kochte, 2016 .