A.H. Banihashemi

An 80-Mb/s 0.18-/spl mu/m CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code

C. Plett, S. Hemati, A.H. Banihashemi, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Irregular rate-compatible LDPC codes for capacity-approaching hybrid-ARQ schemes

M. Yazdani, A.H. Banihashemi, A. Banihashemi, 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code

C. Plett, S. Hemati, A.H. Banihashemi, 2006, IEEE Journal of Solid-State Circuits.