V. Fong

A 64 MHz /spl Sigma//spl Delta/ ADC with 105 dB IM3 distortion using a linearized replica sampling network

T.L. Brooks, S.K. Gupta, V. Fong, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

V. Fong, S. K. Gupta, 2002 .

Direct-conversion CMOS transceiver with automatic frequency control for 802.11a wireless LANs

A. Behzad, A. Rofougaran, Z.M. Shi, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 4.92-5.845 GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN

A. Behzad, A. Rofougaran, Z.M. Shi, 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.