C. Tretz

Double gate (DG)-SOI ratioed logic with symmetric DG load––a novel approach for sub 50 nm low-voltage/low-power circuit design

Souvick Mitra, Akram A. Salman, D. P. Ioannou, 2004 .

Novel high-density low-power high-performance double-gate logic techniques

C. Tretz, Ching-Te Chuang, Keunwoo Kim, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

An efficient macromodel for static CMOS multi-port memories

C. Zukowski, C. Tretz, P. Landsberg, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Novel high-density low-power logic circuit techniques using DG devices

C. Tretz, Ching-Te Chuang, Meng-Hsueh Chiang, 2005, IEEE Transactions on Electron Devices.

Performance comparison of differential static CMOS circuit topologies in SOI technology

C. Tretz, Ching-Te Chuang, L. Terman, 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

Ratioed CMOS: a low power high speed design choice in SOI technologies

C. Tretz, W. Reohr, R. K. Montoye, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Hysteresis in floating-body PD/SOI CMOS circuits

C. Tretz, Ching-Te Chuang, M. M. Pelella, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

Souvick Mitra, C. Tretz, Dimitris E. Ioannou, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

C. Tretz, C. Riccobene, S. P. Sinha, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

C. Tretz, Ching-Te Chuang, Meng-Hsueh Chiang, 2006, IEEE Transactions on Electron Devices.