Eitan N. Shauly

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Eitan N. Shauly, E. Shauly, 2012 .

Experimental extraction of point defects parameters needed for 2-D process modeling using reverse modeling

Eitan N. Shauly, Richard Ghez, Yigal Komem, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Standard cell electrical and physical variability analysis based on automatic physical measurement for design-for-manufacturing purposes

Eitan N. Shauly, Shimon Levi, Ofer Adan, 2011, Advanced Lithography.

MBPCA application for fault detection in NMOS fabrication

Eitan N. Shauly, Daniel R. Lewin, Sivan Lachman-Shalem, 2002 .

Effect of the pLDD implantation dose on pMOS transistor characteristics

Eitan N. Shauly, Yigal Komem, Richard M. Fastow, 1996, Advanced Lithography.

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Eitan N. Shauly, E. Shauly, 2018, Journal of Low Power Electronics and Applications.

Monitoring and characterization of metal-over-contact based edge-contour extraction measurement followed by electrical simulation

Eitan N. Shauly, Shimon Levi, Ishai Schwarzband, 2010, Advanced Lithography.

Fault detection in CMOS manufacturing using MBPCA

Eitan N. Shauly, Daniel R. Lewin, Sivan Lachman-Shalem, 2000, SPIE Advanced Lithography.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

Eitan N. Shauly, Shimon Levi, Ofer Adan, 2015 .

Device performances analysis of standard-cells transistors using silicon simulation and build-in device simulation

Eitan N. Shauly, Allon Parag, Uri Krispil, 2010, Advanced Lithography.