R. Bao

A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

Y. Liu, C. Ortolland, V. Narayanan, 2012, 2012 Symposium on VLSI Technology (VLSIT).

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Differentiated Performance and Reliability Enabled by Multi-Work Function Solution in RMG Silicon and SiGe MOSFETs

T. Ando, R. G. Southwick, V. Narayanan, 2018, 2018 IEEE Symposium on VLSI Technology.

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

C. Park, N. Loubet, B. Haran, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).