J. Muncy

A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

Y. Liu, C. Ortolland, V. Narayanan, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Coal ash by-product reutilization

B. Miller, J. Muncy, 1997 .

High performance bulk planar 20nm CMOS technology for low power mobile applications

O. Menut, Y. Liu, S. Samavedam, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

L. Economikos, Jianping Zheng, J. Muncy, 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

D. Questad, J. Muncy, C. Carey, 2007, 2007 IEEE International Interconnect Technology Conferencee.

Experimental wetting dynamics study of eutectic and lead-free solders with various fluxes, isothermal conditions, and bond pad metallizations

J. Muncy, Chunho Kim, D.F. Baldwin, 2005, IEEE Transactions on Advanced Packaging.