Sanjay Dabral

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency

Jae Choi, Ming Liu, Ben Lee, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

Mahmudul Hassan, Khaldoon Abugharbieh, Chethan Rao, 2014 .

A method of retraining the clock for receiver

Akhilesh Kumar, Sanjay Dabral, Victor San Jose Lee, 2004 .

Method, system and apparatus for managing the connection delay

Michael J. Tripp, Sanjay Dabral, Naveen Cherukuri, 2005 .