Nader Bagherzadeh

发表

Area and power-efficient innovative congestion-aware Network-on-Chip architecture

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, 2011, J. Syst. Archit..

Efficient multicast schemes for 3-D Networks-on-Chip

Yingtao Jiang, Mei Yang, Xiaohang Wang, 2013, J. Syst. Archit..

Performance of symbolic applications on a parallel architecture

Adolfo Guzmán-Arenas, Nader Bagherzadeh, Edward J. Krall, 2005, International Journal of Parallel Programming.

Quantum-dot cellular automata circuits with reduced external fixed inputs

Keivan Navi, Nader Bagherzadeh, Milad Bagherian Khosroshahy, 2017, Microprocess. Microsystems.

Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1998, IEEE Trans. Parallel Distributed Syst..

Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005

Mateo Valero, Nader Bagherzadeh, Alex Ramirez, 2005, Conf. Computing Frontiers.

Parallel implementation of the auction algorithm on the Intel hypercube

Nader Bagherzadeh, Kent Hawk, 1992, Proceedings Sixth International Parallel Processing Symposium.

CompStor: An In-storage Computation Platform for Scalable Distributed Processing

Nader Bagherzadeh, Mahdi Torabzadehkashi, Siavash Rezaei, 2018, 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

On Design and Application Mapping of a Network-on-Chip(NoC) Architecture

Yoon Seok Yang, Seung Eun Lee, Nader Bagherzadeh, 2008, Parallel Process. Lett..

Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs

Keivan Navi, Nader Bagherzadeh, Mohammad Hossein Moaiyeri, 2018, IEEE Transactions on Fuzzy Systems.

Fault-diameter of the star-connected cycles interconnection network

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

An efficient partitioning and scheduling algorithm for streaming applications on FPGA with resource constraint

Nader Bagherzadeh, Radha Guha, 2007 .

ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects

Nader Bagherzadeh, Pooria M. Yaghini, Freek Verbeek, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Recfec: a reconfigurable forward error correction engine

Nader Bagherzadeh, A. Niktash, 2006 .

Communication speed selection for embedded systems with networked voltage-scalable processors

Pai H. Chou, Jinfeng Liu, Nader Bagherzadeh, 2002, CODES '02.

On the design of hybrid routing mechanism for mesh-based network-on-chip

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2015, Integr..

A GALS Router for Asynchronous Network-on-Chip

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2014, MES '14.

LocSens - An Indoor Location Tracking System using Wireless Sensors

Theo Ungerer, Nader Bagherzadeh, Florian Kluge, 2008, 2008 Proceedings of 17th International Conference on Computer Communications and Networks.

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A High Performance, Multi-Bit Output Logic-in-Memory Adder

Nader Bagherzadeh, Hamid R. Zarandi, Javad Talafy, 2021, IEEE Transactions on Emerging Topics in Computing.

Automatic creation of three-dimensional avatars

Falko Kuester, Nader Bagherzadeh, Maria-Cruz Villa-Uriol, 2003, IS&T/SPIE Electronic Imaging.

Performance analysis and design methodology for a scalable superscalar architecture

Nader Bagherzadeh, Takaaki Kato, Toshihisa Ono, 1992, MICRO.

Faster column operations in star networks

Shahram Latifi, Nader Bagherzadeh, Martin Dowd, 1998, Telecommun. Syst..

Optimisations for LocSens - an indoor location tracking system using wireless sensors

Theo Ungerer, Nader Bagherzadeh, Florian Kluge, 2009, Int. J. Sens. Networks.

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip

Masoumeh Ebrahimi, Nader Bagherzadeh, Ronak Salamat, 2015, 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique

Nader Bagherzadeh, Hesham Eldeeb, Hala Elsadek, 2008, Communications in Computing.

Simulation-Based Evaluation Strategy for Task Mapping Approaches in WNoC Platforms

Nader Bagherzadeh, Luis German Garcia Morales, Jose Edinson Aedo Cobo, 2018, 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).

A formal approach to context scheduling for multicontext reconfigurable architectures

Román Hermida, Nader Bagherzadeh, Rafael Maestre, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Pyramid simulation of image processing applications

Nader Bagherzadeh, S. Shoari, Alireza Kavianpour, 1993 .

Computation of the fast fourier transform on the star-connected cycle networks

Nader Bagherzadeh, S. Shoari, 1996 .

A study of star graph algorithms

Nader Bagherzadeh, Nayla Nassif, 1996 .

Power-Aware Scheduling under Timing Constraints and Slack Analysis for Mission-Critical Embedded Systems

Fadi J. Kurdahi, Jinfeng Liu, Pai H. Chou, 2001 .

Design and implementation of a 100 MHz reorder buffer

Nader Bagherzadeh, Steven D. Wallace, N. Dagli, 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

A Component Oriented Simulator for HW/SW Co-Designs

Nader Bagherzadeh, Haitao Du, Alexander Paar, 2003, ESTImedia.

A fast algorithm for parallel computation of multibody dynamics on MIMD parallel architectures

Amir Fijany, Nader Bagherzadeh, Gregory L. Kwan, 1993 .

High-throughput differentiated service provision router architecture for wireless network-on-chip

Chifeng Wang, Nader Bagherzadeh, 2012, Int. J. High Perform. Syst. Archit..

Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems

Nader Bagherzadeh, Afshin Niktash, Hooman Parizi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system

Pai H. Chou, Nader Bagherzadeh, Radha Guha, 2009, Comput. Electr. Eng..

Divisible Load Scheduling of Image Processing Applications on the Heterogeneous Star Network Using a new Genetic Algorithm

Nader Bagherzadeh, Sahar Nikbakht Aali, Hadi Shahriar Shahhosseini, 2018, 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).

Topology selection for energy minimization in embedded networks

Pai H. Chou, Nader Bagherzadeh, Dexin Li, 2003, ASP-DAC '03.

A formally verified deadlock-free routing function in a fault-tolerant NoC architecture

Julien Schmaltz, Nader Bagherzadeh, Freek Verbeek, 2012, 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI).

Design and Analysis of a Mesh-based Wireless Network-on-Chip

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, 2012, PDP.

Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform

Seung Eun Lee, Nader Bagherzadeh, Jungsook Yang, 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

KINEMATIC SYNTHESIS OF AVATAR SKELETONS FROM VISUAL DATA

Falko Kuester, J. Michael McCarthy, Nader Bagherzadeh, 2004 .

Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks

Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh, 2020, 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

VIPER: a VLIW integer microprocessor

Nader Bagherzadeh, J. Gray, A. Naylor, 1993 .

Design and analysis of on-chip interconnection network for multi-processor system-on-chip

Seung Eun Lee, Nader Bagherzadeh, 2008 .

An approach to execute conditional branches onto SIMD multi-context reconfigurable architectures

Nader Bagherzadeh, Milagros Fernández, Fredy Rivera, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Flow mapping and data distribution on mesh-based deep learning accelerator

Midia Reshadi, Hesam Shabani, Xiaochen Guo, 2019, NOCS.

A scheduling approach for distributed resource architectures with scarce communication resources

Nader Bagherzadeh, Akira Hatanaka, N. Bagherzadeh, 2011, Int. J. High Perform. Syst. Archit..

Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm

Ahmad Khademzadeh, Majid Janidarmian, Nader Bagherzadeh, 2013, 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Finding elliptical shapes in an image using a pyramid architecture

Nader Bagherzadeh, S. Shoari, Alireza Kavianpour, 1995 .

An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata

Keivan Navi, Nader Bagherzadeh, Milad Bagherian Khosroshahy, 2017 .

Automatic compilation to a coarse-grained reconfigurable system-opn-chip

Fadi J. Kurdahi, Nader Bagherzadeh, Girish Venkataramani, 2003, TECS.

A Framework for Reconfigurable Computing: Task Scheduling and Context Management— A Summary A Framework for Reconfigurable Computing: Task Scheduling and Context Management—

Fadi J. Kurdahi, Nader Bagherzadeh, Rafael Maestre, 2002 .

A scalable register file architecture for dynamically scheduled processors

Nader Bagherzadeh, Steven Wallace, 1996, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique.

Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs

Michael M. Green, Nader Bagherzadeh, Pooria M. Yaghini, 2016, IEEE Transactions on Computers.

Voltage island based heterogeneous NoC design through constraint programming

Ayhan Demiriz, Nader Bagherzadeh, Özcan Özturk, 2014, Comput. Electr. Eng..

Special issue on: On-chip parallel and network-based systems

Hamid Sarbazi-Azad, Nader Bagherzadeh, 2011, J. Syst. Archit..

Novel CNFET ternary circuit techniques for high-performance and energy-efficient design

Keivan Navi, Sepehr Tabrizchi, Nader Bagherzadeh, 2019, IET Circuits Devices Syst..

Multicore computing systems: Architecture, programming tools, and applications

Hamid Sarbazi-Azad, Nader Bagherzadeh, 2013, J. Comput. Syst. Sci..

AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs

Nader Bagherzadeh, Zana Ghaderi, Ayed Alqahtani, 2018, IEEE Transactions on Parallel and Distributed Systems.

NoC Design Methodologies for Heterogeneous Architecture

Masoomeh Jasemi, Nader Bagherzadeh, Lulwah Alhubail, 2020, 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

Design and implementation of the 'Tiny RISC' microprocessor

Nader Bagherzadeh, Arthur Abnous, Christopher Christensen, 1992, Microprocess. Microsystems.

Ultra-low-power adder stage design for exascale floating point units

Román Hermida, Nader Bagherzadeh, Alberto A. Del Barrio, 2014, ACM Trans. Embed. Comput. Syst..

A Novel Predication Scheme for a SIMD System-on-Chip

Manuel Lois Anido, Nader Bagherzadeh, M. L. Anido, 2002, Euro-Par.

A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks

Nader Bagherzadeh, Hyun-Jin Kim, Alberto A. Del Barrio, 2019, 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH).

A constraint-based application model and scheduling techniques for power-aware systems

Fadi J. Kurdahi, Pai H. Chou, Jinfeng Liu, 2001, CODES '01.

Optimal ring embedding in hypercubes with faulty links

Shahram Latifi, Si-Qing Zheng, Nader Bagherzadeh, 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources

Pai H. Chou, Jinfeng Liu, Nader Bagherzadeh, 2002, PACS.

Using constraint programming for the design of network-on-chip architectures

Ayhan Demiriz, Nader Bagherzadeh, Abdulaziz Alhussien, 2013, Computing.

Integrated Management of Power Aware Computation and Communication (IMPACCT)

Pai H. Chou, Nader Bagherzadeh, 2003 .

MorphoSys: An Integrated Re-configurable Architecture

Fadi J. Kurdahi, Nader Bagherzadeh, Guangming Lu, 2000 .

Morphosys: case study of a reconfigurable computing system targeting multimedia applications

Fadi J. Kurdahi, Guangming Lu, Nader Bagherzadeh, 2000, Proceedings 37th Design Automation Conference.

A data scheduler for multi-context reconfigurable architectures

Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh, 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

Method for designing ternary adder cells based on CNFETs

Keivan Navi, Fazel Sharifi, Sepehr Tabrizchi, 2017, IET Circuits Devices Syst..

A high level power model for Network-on-Chip (NoC) router

Seung Eun Lee, Nader Bagherzadeh, 2009, Comput. Electr. Eng..

Design of quaternary 4-2 and 5-2 compressors for nanotechnology

Keivan Navi, Fazel Sharifi, Himanshu Thapliyal, 2016, Comput. Electr. Eng..

A New Approach for Circle Detection on Multiprocessors

Nader Bagherzadeh, S. Shoari, Alireza Kavianpour, 1994, J. Parallel Distributed Comput..

Near-optimal message routing and broadcasting in faulty hypercubes

Douglas M. Blough, Nader Bagherzadeh, 2005, International Journal of Parallel Programming.

Low energy data management for different on-chip memory levels in multi-context reconfigurable architectures

Román Hermida, Manuel Lois Anido, Nader Bagherzadeh, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Coupling Mitigation in 3-D Multiple-Stacked Devices

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficient Mitchell’s Approximate Log Multipliers for Convolutional Neural Networks

Nader Bagherzadeh, Min Soo Kim, Alberto A. Del Barrio, 2019, IEEE Transactions on Computers.

Parallel Algorithms for Line Detection on A Pyramid Architecture

Nader Bagherzadeh, Alireza Kavianpour, 1994, Int. J. Pattern Recognit. Artif. Intell..

From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations

Nader Bagherzadeh, Fredy Rivera, Freddy Bolanos, 2013, J. Syst. Archit..

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

Fadi J. Kurdahi, Nader Bagherzadeh, Girish Venkataramani, 2001, CASES '01.

A Generic Network Interface Architecture for a Networked Processor Array (NePA)

Yoon Seok Yang, Seung Eun Lee, Nader Bagherzadeh, 2008, ARCS.

CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture

Ahmad Khademzadeh, Nader Bagherzadeh, Midia Reshadi, 2019, J. Syst. Archit..

An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs

Keivan Navi, Nader Bagherzadeh, Mohammad Hossein Moaiyeri, 2016, J. Low Power Electron..

STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs

Nader Bagherzadeh, Zana Ghaderi, Ahmad Albaqsami, 2018, IEEE Transactions on Computers.

Fast and efficient voltage scheduling by evolutionary slack distribution

Pai H. Chou, Nader Bagherzadeh, David W. Jensen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Chifeng Wang, Nader Bagherzadeh, 2014, Microprocess. Microsystems.

A Reconfigurable Architecture for Wireless Communication Systems

Nader Bagherzadeh, Afshin Niktash, Hooman Parizi, 2006, Third International Conference on Information Technology: New Generations (ITNG'06).

IMPACCT: Methodology and Tools for Power-Aware Embedded Systems

Pai H. Chou, Jinfeng Liu, Nader Bagherzadeh, 2002, Des. Autom. Embed. Syst..

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2015, IEEE Transactions on Computers.

RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding

Nader Bagherzadeh, Afshin Niktash, Hooman Parizi, 2008, 2008 IEEE Wireless Communications and Networking Conference.

Interactive ray tracing using a SIMD reconfigurable architecture

Nozar Tabrizi, Manuel Lois Anido, Nader Bagherzadeh, 2002, 14th Symposium on Computer Architecture and High Performance Computing, 2002. Proceedings..

A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template

Nader Bagherzadeh, Akira Hatanaka, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Guest Editors' Introduction: Configurable Computing

Fadi J. Kurdahi, Jose L. Muñoz, Peter M. Athanas, 2000, IEEE Des. Test Comput..

Erratic non-uniform traffic behavior of a multiple microcomputer network

Chuan-lin Wu, Nader Bagherzadeh, Ken Tseng, 1988 .

Area and Power-efficient Innovative Network-on-Chip Architecurte

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, 2010, 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing.

The clustered-star graph: a new topology for large interconnection networks

Shahram Latifi, Nader Bagherzadeh, 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip

Nacer-Eddine Zergainoh, Masoumeh Ebrahimi, Nader Bagherzadeh, 2018, IEEE Transactions on Computers.

On heterogeneous network-on-chip design based on constraint programming

Ayhan Demiriz, Nader Bagherzadeh, 2013, NoCArc '13.

MaRS: a macro-pipelined reconfigurable system

Nozar Tabrizi, Nader Bagherzadeh, Haitao Du, 2004, CF '04.

Deadlock Verification of Cache Coherence Protocols and Communication Fabrics

Nader Bagherzadeh, Pooria M. Yaghini, Freek Verbeek, 2017, IEEE Transactions on Computers.

HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors

Nader Bagherzadeh, Ahmad Albaqsami, Maryam S. Hosseini, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Optimal vs. heuristic approaches to context scheduling for multi-context reconfigurable architectures

Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh, 2000, Proceedings 2000 International Conference on Computer Design.

MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

Fadi J. Kurdahi, Guangming Lu, Nader Bagherzadeh, 2000, IEEE Trans. Computers.

A framework for scheduling and context allocation in reconfigurable computing

Román Hermida, Nader Bagherzadeh, Rafael Maestre, 1999, Proceedings 12th International Symposium on System Synthesis.

Design and implementation of Automatic Parallel Detection Layer

Nader Bagherzadeh, Hesham Eldeeb, Salwa M. Nassar, 2001, 2001 IEEE International Conference on Systems, Man and Cybernetics. e-Systems and e-Man for Cybernetics in Cyberspace (Cat.No.01CH37236).

Embedding an Arbitrary Binary Tree into the Star Graph

Nader Bagherzadeh, Martin Dowd, Nayla Nassif, 1996, IEEE Trans. Computers.

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Keivan Navi, Sepehr Tabrizchi, Nader Bagherzadeh, 2019 .

Three-dimensional modeling from images and video streams

Nader Bagherzadeh, Miguel Sainz, 2003 .

High-performance ternary operators for scrambling

Keivan Navi, Nader Bagherzadeh, Reza Faghih Mirzaee, 2017, Integr..

A Wireless Network-on-Chip Design for Multicore Platforms

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

Macropipelined multicomputer architecture for image analysis

Nader Bagherzadeh, Jack Sklansky, Young Shik Moon, 1989 .

A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture

Nader Bagherzadeh, Afshin Niktash, Hooman Parizi, 2006, IEEE Vehicular Technology Conference.

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)

Seung Eun Lee, Nader Bagherzadeh, Jun Ho Bahn, 2007, 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07).

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)

Seung Eun Lee, Nader Bagherzadeh, Jun Ho Bahn, 2007 .

Design and analysis of a programmable single-chip architecture for DVB-T base-band receiver

Nader Bagherzadeh, Arezou Koohi, Amir Hosein Kamalizad, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform

Wen-Hsiang Hu, Nader Bagherzadeh, Jun Ho Bahn, 2009, 2009 21st International Symposium on Computer Architecture and High Performance Computing.

Optimal vs. heuristic approaches to context scheduling for multi-context reconfigurable architectures

Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh, 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

Finding circular shapes in an image on a pyramid architecture

Nader Bagherzadeh, Alireza Kavianpour, 1992, Pattern Recognit. Lett..

Scalable load balancing congestion-aware Network-on-Chip router architecture

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, 2013, J. Comput. Syst. Sci..

Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip

Nader Bagherzadeh, Masaru Matsuura, 2008, Fifth International Conference on Information Technology: New Generations (itng 2008).

On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture

Seung Eun Lee, Nader Bagherzadeh, Jun Ho Bahn, 2007, Fourth International Conference on Information Technology (ITNG'07).

Plasmonic detection of possible defects in multilayer nanohole array consisting of essential materials in simplified STT-RAM cell

Ilya Krivorotov, Qiancheng Zhao, Nader Bagherzadeh, 2017, NanoScience + Engineering.

The MorphoSys Parallel Reconfigurable System

Fadi J. Kurdahi, Guangming Lu, Nader Bagherzadeh, 1999, Euro-Par.

Average distance and routing algorithms in the star-connected cycles interconnection network

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1996, Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing.

Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router

Nader Bagherzadeh, Jun Ho Bahn, 2008, IET Comput. Digit. Tech..

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics

Hossein Bobarshad, Nader Bagherzadeh, Mahdi Torabzadehkashi, 2019, 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

Design and analysis of network-on-chip (noc) architecture

Nader Bagherzadeh, Jun Ho Bahn, 2008 .

An efficient placement algorithm for run-time reconfigurable embedded system

Pai H. Chou, Nader Bagherzadeh, Radha Guha, 2007 .

Design and Implementation of the MorphoSys Reconfigurable Computing Processor

Fadi J. Kurdahi, Guangming Lu, Nader Bagherzadeh, 2000, J. VLSI Signal Process..

Pipelining and Bypassing in a VLIW Processor

Nader Bagherzadeh, A. Abnous, 1994, IEEE Trans. Parallel Distributed Syst..

CoBRA: Low cost compensation of TSV failures in 3D-NoC

Masoumeh Ebrahimi, Nader Bagherzadeh, Freek Verbeek, 2016, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Parallel FFT Algorithms on Network-on-Chips

Wen-Hsiang Hu, Nader Bagherzadeh, Jun Ho Bahn, 2008, Fifth International Conference on Information Technology: New Generations (itng 2008).

Combined functional partitioning and communication speed selection for networked voltage-scalable processors

Pai H. Chou, Jinfeng Liu, Nader Bagherzadeh, 2002, 15th International Symposium on System Synthesis, 2002..

Ray tracing on a networked processor array

Seung Eun Lee, Nader Bagherzadeh, Jungsook Yang, 2010 .

Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)

Nader Bagherzadeh, Marcos Sanchez-Elez, Javier Davila, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Performance study of a multithreaded superscalar microprocessor

Nader Bagherzadeh, Manu Gulati, N. Bagherzadeh, 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.

A software pipelining algorithm of streaming applications with low buffer requirements

Nader Bagherzadeh, A. Hatanaka, 2012, Sci. Iran..

A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs

Nader Bagherzadeh, J. E. Aedo Cobo, L. G. García Morales, 2019, J. Syst. Archit..

A Well-Behaved Enumeration of Star Graphs

Shahram Latifi, Nader Bagherzadeh, Martin Dowd, 1995, IEEE Trans. Parallel Distributed Syst..

System-Level Analysis of 3D ICs with Thermal TSVs

Jaeho Lee, Nader Bagherzadeh, Ayed Alqahtani, 2018, ACM J. Emerg. Technol. Comput. Syst..

Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures

Román Hermida, Nader Bagherzadeh, Marcos Sanchez-Elez, 2008, IET Comput. Digit. Tech..

Design and implementation of parallel algorithms for medical imaging applications

Nader Bagherzadeh, Simin Shoari, 1998 .

Congestion-aware Network-on-Chip router architecture

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks

Ronald F. DeMara, Hesam Shabani, Nader Bagherzadeh, 2016, IEEE Transactions on Computers.

On clustered-star graph and its properties

Shahram Latifi, Nader Bagherzadeh, 1996 .

A Spectral-based partitioning algorithm for parallel LDPC decoding on a multiprocessor platform

Wen-Hsiang Hu, Nader Bagherzadeh, Chun-Yi Chen, 2009, 2009 International SoC Design Conference (ISOCC).

VIPER: A 25-MHz, 100-MIPS peak VLIW microprocessor

Nader Bagherzadeh, A. Naylor, A. Abnous, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification

Masoumeh Ebrahimi, Nader Bagherzadeh, Misagh Khayambashi, 2018, IEEE Transactions on Computers.

On-chip parallel and network-based systems

Hamid Sarbazi-Azad, Masoud Daneshtalab, Nader Bagherzadeh, 2015, Integr..

Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture

Nader Bagherzadeh, Jun Ho Bahn, 2008 .

Recovering 3D metric structure and motion from multiple uncalibrated cameras

Nader Bagherzadeh, Antonio Susín, Miguel Sainz, 2002, Proceedings. International Conference on Information Technology: Coding and Computing.

IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes

Alireza Tajary, Nader Bagherzadeh, Hamid R. Zarandi, 2020, Microprocess. Microsystems.

A programmable DSP architecture for wireless communication systems

Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

Camera calibration of long image sequences with the presence of occlusions

Nader Bagherzadeh, Antonio Susín, Miguel Sainz, 2003, Proceedings 2003 International Conference on Image Processing (Cat. No.03CH37429).

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

Pai H. Chou, Nader Bagherzadeh, Bita Gorjiara, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Application of three-valued logic for distributed termination detection

Nader Bagherzadeh, Alireza Kavianpour, 1991 .

Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors

Nader Bagherzadeh, Steven Wallace, 1998, IEEE Trans. Parallel Distributed Syst..

Pipelining and Bypassing in a VLIW Processor

Nader Bagherzadeh, A. Abnous, N. Bagherzadeh, 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata

Keivan Navi, Nader Bagherzadeh, Milad Bagherian Khosroshahy, 2019, International Journal of Information Technology.

Architectural Design and Analysis of a VLIW Processor

Nader Bagherzadeh, A. Abnous, N. Bagherzadeh, 1995 .

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

Román Hermida, Nader Bagherzadeh, Min Soo Kim, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs

Keivan Navi, Nader Bagherzadeh, Reza Faghih Mirzaee, 2017, J. Multiple Valued Log. Soft Comput..

A Systematic Approch for Mapping Application Tasks in Hypercubes

Nader Bagherzadeh, Alireza Kavianpour, 1993, IEEE Trans. Computers.

Mode selection and mode-dependency modeling for power-aware embedded systems

Pai H. Chou, Nader Bagherzadeh, Dexin Li, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

A fine-grain multithreading superscalar architecture

Nader Bagherzadeh, M. Loikkanen, 1996, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique.

A Routing and Broadcasting Scheme on Faulty Star Graphs

Shahram Latifi, Nader Bagherzadeh, Nayla Nassif, 1993, IEEE Trans. Computers.

Capacitive Coupling Mitigation for TSV-based 3D ICs

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder

Keivan Navi, Nader Bagherzadeh, Shaahin Angizi, 2015, J. Low Power Electron..

Message Driven Programming with S-Net: Methodology and Performance

Alexander V. Shafarenko, Clemens Grelck, Sven-Bodo Scholz, 2010, 2010 39th International Conference on Parallel Processing Workshops.

DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems

Ahmad Khademzadeh, Nader Bagherzadeh, Midia Reshadi, 2019, IET Comput. Digit. Tech..

A scalable delay insensitive asynchronous NoC with adaptive routing

Chifeng Wang, Nader Bagherzadeh, Abdulaziz Alhussien, 2010, 2010 17th International Conference on Telecommunications.

A framework for low energy data management in reconfigurable multi-context architectures

Román Hermida, Nader Bagherzadeh, Marcos Sanchez-Elez, 2009, J. Syst. Archit..

An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator

Nozar Tabrizi, Nader Bagherzadeh, N. Bagherzadeh, 2008, Integr..

Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations

Fadi J. Kurdahi, Nader Bagherzadeh, Rafael Maestre, 2000, ISSS '00.

Introduction to the Special Section on On-chip parallel and network-based systems

Hamid Sarbazi-Azad, Masoud Daneshtalab, Nader Bagherzadeh, 2016, Comput. Electr. Eng..

Incomplete Star: An Incrementally Scalable Network Based on the Star Graph

Shahram Latifi, Nader Bagherzadeh, N. Bagherzadeh, 1994, IEEE Trans. Parallel Distributed Syst..

Fast parallel FFT on a reconfigurable computation platform

Nader Bagherzadeh, Amir Hosein Kamalizad, Chengzhi Pan, 2003, Proceedings. 15th Symposium on Computer Architecture and High Performance Computing.

Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost

Pai H. Chou, Nader Bagherzadeh, Bita Gorjiara, 2007, 2007 Asia and South Pacific Design Automation Conference.

Pyramid simulation of image processing applications

Nader Bagherzadeh, S. Shoari, Alireza Kavianpour, 1994, Image Vis. Comput..

A high-performance fully programmable membership function generator based on 10 nm gate-all-around CNTFETs

Nader Bagherzadeh, Mohammad Hossein Moaiyeri, Ali Bozorgmehr, 2020 .

Advances in multicore systems architectures

Hamid Sarbazi-Azad, Nader Bagherzadeh, G. Jaberipour, 2015, The Journal of Supercomputing.

Software Authorization Systems

Nader Bagherzadeh, Neil Iscoe, Paul A. Suhler, 1986, IEEE Software.

Multi-level Security in Wireless Sensor Networks

Theo Ungerer, Nader Bagherzadeh, Faruk Bagci, 2009 .

Proceedings of the 2nd conference on Computing frontiers

Mateo Valero, Nader Bagherzadeh, Alex Ramirez, 2005, CF 2008.

A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors

Nader Bagherzadeh, Mohammad Hossein Moaiyeri, Ali Bozorgmehr, 2020, Comput. Electr. Eng..

A variable frequency link for a power-aware network-on-chip (NoC)

Seung Eun Lee, Nader Bagherzadeh, 2009, Integr..

MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application

Fadi J. Kurdahi, Guangming Lu, Nader Bagherzadeh, 1999, IPPS/SPDP Workshops.

Instruction Fetching Mechanisms for Superscalar Microprocessors

Nader Bagherzadeh, Steven Wallace, 1996, Euro-Par, Vol. II.

Design and analysis of a mesh-based wireless network-on-chip

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, 2012, 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing.

Accelerating HPC Applications Using Computational Storage Devices

Nader Bagherzadeh, Mahdi Torabzadehkashi, Siavash Rezaei, 2019, 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS).

Ultra-low-power carbon nanotube FET-based quaternary logic gates

Keivan Navi, Fazel Sharifi, Nader Bagherzadeh, 2016 .

Editorial notes: Special issue on on-chip parallel and network-based systems

Hamid Sarbazi-Azad, Nader Bagherzadeh, 2012, Microprocess. Microsystems.

Multiple branch and block prediction

Nader Bagherzadeh, Steven Wallace, N. Bagherzadeh, 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

SecSens - Security Architecture for Wireless Sensor Networks

Theo Ungerer, Nader Bagherzadeh, Faruk Bagci, 2009, 2009 Third International Conference on Sensor Technologies and Applications.

On Embedding Rings into a Star-Related Network

Shahram Latifi, Nader Bagherzadeh, 1997, Inf. Sci..

On the design of fully symmetrical bridge-style circuits

Masoomeh Jasemi, Nader Bagherzadeh, Ali Valizadeh, 2016 .

A Distributed andShared Register File foraMultiprocessor-on-Chip

Nader Bagherzadeh, 2006 .

The Star Connected Cycles: A Fixed-Degree Network For Parallel Processing

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Increasing the throughput of an adaptive router in network-on-chip (NoC)

Seung Eun Lee, Nader Bagherzadeh, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

Self-optimized Routing in a Network on-a-Chip

Wolfgang Trumler, Theo Ungerer, Nader Bagherzadeh, 2008, BICC.

High performance parallel computing for FDTD numerical technique in electromagnetic calculations for SAR distribution inside human head

Nader Bagherzadeh, Hesham Eldeeb, Hala Elsadek, 2010 .

Effect of Tantalum and MgO adhesion layers on plasmonic nanostructures

Nader Bagherzadeh, Mohammad Wahiduzzaman Khan, Parinaz Sadri-Moshkenani, 2019, NanoScience + Engineering.

Fault-Tolerant Optimization for Application-Specific Network-on-Chip Architecture

Ahmad Khademzadeh, Majid Janidarmian, Nader Bagherzadeh, 2014 .

A complete data scheduler for multi-context reconfigurable architectures

Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures

Nader Bagherzadeh, Marcos Sanchez-Elez, Fredy Rivera, 2007, ERSA.

Adaptive computing: what can it do, where can it go?

Toshiaki Miyazaki, Jose L. Muñoz, Prithviraj Banerjee, 2003, ASP-DAC '03.

VLSI transactions best paper award "A framework for reconfigurable computing: task scheduling and context management"

Fadi J. Kurdahi, Nader Bagherzadeh, Rafael Maestre, 2002 .

Hardware Accelerated Voxel Carving

Nader Bagherzadeh, Antonio Susín, Miguel Sainz, 2002 .

Power-aware scheduling under timing constraints for mission-critical embedded systems

Fadi J. Kurdahi, Pai H. Chou, Jinfeng Liu, 2001, DAC '01.

Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits

Nader Bagherzadeh, Jaeho Lee, Zongqing Ren, 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Optimization of parallel ray tracing on memory-bandwidth-constrained systems

Nader Bagherzadeh, Haitao Du, 2004 .

Modeling, implementation and scalability of the morphosys dynamically reconfigurable computing architecture

Fadi J. Kurdahi, Nader Bagherzadeh, Guangming Lu, 2000 .

Some Topological Properties of Star Connected Cycles

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1996, Inf. Process. Lett..

High-Efficient Circuits for Ternary Addition

Keivan Navi, Nader Bagherzadeh, Reza Faghih Mirzaee, 2014, VLSI Design.

A framework for reconfigurable computing: task scheduling and context management

Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip

Nader Bagherzadeh, Masaru Matsuura, 2008, ITNG.

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

Keivan Navi, Arman Roohi, Nader Bagherzadeh, 2015, J. Circuits Syst. Comput..

A Machine Learning Approach to Predict Hypotensive Events in ICU Settings

Nader Bagherzadeh, Guann-Pyng Li, Mina Chookhachizadeh Moghadam, 2019, bioRxiv.

Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology

Keivan Navi, Nader Bagherzadeh, MohammadReza Taheri, 2019, Microelectron. J..

Towards Approximate Computing with Quantum-Dot Cellular Automata

Keivan Navi, Nader Bagherzadeh, Shaahin Angizi, 2017, J. Low Power Electron..

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption

Nader Bagherzadeh, Shaahin Angizi, Deliang Fan, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Special issue on on-chip parallel and network-based systems

Hamid Sarbazi-Azad, Masoud Daneshtalab, Nader Bagherzadeh, 2015, Computing.

Parallel processing for block ciphers on a fault tolerant networked processor array

Yoon Seok Yang, Seung Eun Lee, Nader Bagherzadeh, 2010, Int. J. High Perform. Syst. Archit..

Hamiltonicity of the Clustered-Star Graph with Embedding Applications

Shahram Latifi, Nader Bagherzadeh, 1996, PDPTA.

Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators

Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh, 2020, Comput. Electr. Eng..

A novel method for improving the operation autonomy of SIMD processing elements

Manuel Lois Anido, Nader Bagherzadeh, M. L. Anido, 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

Image processing applications in C++ on a hypercube multicomputer

Nader Bagherzadeh, Connie Bowen, 1993 .

Distributed resource management: garbage collection

Nader Bagherzadeh, 1987 .

Adaptive HTF-MPR

Masoomeh Jasemi, Nader Bagherzadeh, Ahmad Albaqsami, 2020, ACM Transactions on Intelligent Systems and Technology.

Application partitioning and mapping for bypass channel based NoC

Nader Bagherzadeh, Midia Reshadi, Fatemeh Khodaparast, 2018, Comput. Electr. Eng..

A Grid Embedding into the Star Graph for Image Analysis Solutions

Nader Bagherzadeh, Nayla Nassif, 1996, Inf. Process. Lett..

Fully Reliable Dynamic Routing Logic for a Fault-Tolerant NoC Architecture

Julien Schmaltz, Nader Bagherzadeh, Freek Verbeek, 2013 .

Design and implementation of the high-performance low-power morphosys reconfigurable processor

Fadi J. Kurdahi, Nader Bagherzadeh, Ming-Hau Lee, 2000 .

An energy and area efficient 4: 2 compressor based on FinFETs

Keivan Navi, Nader Bagherzadeh, Mohammad Hossein Moaiyeri, 2018, Integr..

Data cache architecture of the superscalar by scheduling patterns

Nader Bagherzadeh, T. Kato, T. Ono, 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing

Nader Bagherzadeh, Wei Kang Tsai, Young C. Kim, 1991, ICPP.

Macropipelined Multicomputer Systems For Image Analysis

Nader Bagherzadeh, Jack Sklansky, Young Shik Moon, 1989, Photonics West - Lasers and Applications in Science and Engineering.

A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates

Keivan Navi, Nader Bagherzadeh, Reza Faghih Mirzaee, 2017, IET Circuits Devices Syst..

A performance comparison of several superscalar processor models with a VLIW processor

Nader Bagherzadeh, John Lenell, 1994, Microprocess. Microsystems.

Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling

Pai H. Chou, Nader Bagherzadeh, Bita Gorjiara, 2007, TODE.

Video-based avatar reconstruction and motion capture

Falko Kuester, Nader Bagherzadeh, Maria Cruz Villa Uriol, 2005 .

A multiprocessor array architecture for dsp and wireless applications and case study of an ieee 802.11a receiver implementation

Nader Bagherzadeh, Amir Hosein Kamalizad, 2006 .

Analytical Reliability Analysis of 3D NoC under TSV Failure

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2015, ACM J. Emerg. Technol. Comput. Syst..

A Compositional Approach for Verifying Protocols Running on On-Chip Networks

Nader Bagherzadeh, Pooria M. Yaghini, Freek Verbeek, 2018, IEEE Transactions on Computers.

Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation

Ali Ahmadinia, Nader Bagherzadeh, Michael Opoku Agyeman, 2016, IEEE Transactions on Parallel and Distributed Systems.

Contention-aware selection strategy for application-specific network-on-chip

Ahmad Khademzadeh, Majid Janidarmian, Nader Bagherzadeh, 2013, IET Comput. Digit. Tech..

Scheduling Techniques for Multi-Core Architectures

Nader Bagherzadeh, Akira Hatanaka, 2009, 2009 Sixth International Conference on Information Technology: New Generations.

Energy and Power Issues in Networks-on-Chips

Seung Eun Lee, Nader Bagherzadeh, 2009 .

Parallel Hough Transform for Image Processing on a Pyramid Architecture

Nader Bagherzadeh, Alireza Kavianpour, 1991, ICPP.

Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata

Keivan Navi, Esam Alkaldy, Nader Bagherzadeh, 2014, J. Low Power Electron..

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Yoon Seok Yang, Seung Eun Lee, Nader Bagherzadeh, 2009, 2009 Sixth International Conference on Information Technology: New Generations.

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs

Mohammad Ebrahimi, Zainalabedin Navabi, Nader Bagherzadeh, 2017, IEEE Transactions on Computers.

Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1995, J. Parallel Distributed Comput..

FDTD ACCELERATOR FOR CALCULATING SAR DISTRIBUTION INDSIE HUMAN HEAD DUE TO RADIATION FROM WORELESS DEVICES

Nader Bagherzadeh, Hesham Eldeeb, Hala Elsadek, 2007 .

Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach

Keivan Navi, Fazel Sharifi, Nader Bagherzadeh, 2015, Microelectron. J..

Fast and efficient voltage scheduling by evolutionary slack distribution

Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, 2004 .

Performance issues of a superscalar microprocessor

Nader Bagherzadeh, Steven Wallace, 1995, Microprocess. Microsystems.

Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture

Nozar Tabrizi, Yun Long, Nader Bagherzadeh, 2003, Comput. Graph..

Network Facility for a Reconfigurable Computer Architecture

Geoffrey Brown, Chuan-lin Wu, Nader Bagherzadeh, 1985, ICDCS.

Parallel FFT Algorithms on Network-on-Chips

Nader Bagherzadeh, Jun Ho Bahn, Jungsook Yang, 2008, ITNG.

A star-based I/O-bounded network for massively parallel systems

Shahram Latifi, Nader Bagherzadeh, Marcelo M. de Azevedo, 1995 .

Ternary cyclic redundancy check by a new hardware-friendly ternary operator

Keivan Navi, Nader Bagherzadeh, Reza Faghih Mirzaee, 2016, Microelectron. J..

A Reconfigurable Processor for Forward Error Correction

Nader Bagherzadeh, Afshin Niktash, Hooman Parizi, 2007, ARCS.

Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip

Chifeng Wang, Nader Bagherzadeh, 2012, 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing.

Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata

Keivan Navi, Nader Bagherzadeh, Milad Bagherian Khosroshahy, 2018, J. Low Power Electron..

Hospital enterprise Architecture Framework (Study of Iranian University Hospital Organization)

Hossein Bobarshad, Nader Bagherzadeh, Mohammad Sadegh Rezaei, 2018, Int. J. Medical Informatics.

Low power adaptive pipeline based on instruction isolation

Ming Zhang, Chris Wilkerson, Shih-Lien Lu, 2009, 2009 10th International Symposium on Quality Electronic Design.

A fast parallel Reed-Solomon decoder on a reconfigurable architecture

Nader Bagherzadeh, Arezou Koohi, Chengzhi Pan, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning

Nader Bagherzadeh, Fredy Rivera, Freddy Bolanos, 2012, J. Univers. Comput. Sci..

Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform

Nader Bagherzadeh, Jun Ho Bahn, W.-H. Hu, 2012, IET Comput. Digit. Tech..

Interactive ray tracing on reconfigurable SIMD morphosys

Nozar Tabrizi, Manuel Lois Anido, Nader Bagherzadeh, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Gas-leak localization using distributed ultrasonic sensors

Lubomir Bic, Michael B. Dillencourt, Nader Bagherzadeh, 2009, Smart Structures and Materials + Nondestructive Evaluation and Health Monitoring.

Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures

Román Hermida, Nader Bagherzadeh, Marcos Sanchez-Elez, 2006, 2006 International Conference on Field Programmable Logic and Applications.

A Percolation Based VLIW Architecture

Alexandru Nicolau, Nader Bagherzadeh, Roni Potasman, 1991, ICPP.

Efficient Deep Neural Networks for Edge Computing

Nader Bagherzadeh, Mohammed Alnemari, 2019, 2019 IEEE International Conference on Edge Computing (EDGE).

A parallel algorithm for pulsed laser infrared tomography

Thomas E. Milner, Nader Bagherzadeh, S. Shoari, 1998, Pattern Recognit. Lett..

Vlsi Design Of The Tiny Risc Microprocessor

Nader Bagherzadeh, J. Gray, A. Naylor, 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

Reducing bypass-based network-on-chip latency using priority mechanism

Nader Bagherzadeh, Midia Reshadi, Amir Fadakar Noghondar, 2018, IET Comput. Digit. Tech..

Communication Speed Selection and Functional Partitioning for Low-Energy On-Chip Networked Multiprocessor

Pai H. Chou, Jinfeng Liu, Nader Bagherzadeh, 2002 .

LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC

Ahmad Khademzadeh, Majid Janidarmian, Nader Bagherzadeh, 2012, 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing.

Improving the operation autonomy of SIMD processing elements by using guarded instructions and pseudo branches

Manuel Lois Anido, Nader Bagherzadeh, M. L. Anido, 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing

Shahram Latifi, Nader Bagherzadeh, Marcelo Moraes de Azevdeo, 1996, Euro-Par, Vol. I.

MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note)

Fadi J. Kurdahi, Nader Bagherzadeh, Afshin Niktash, 2002, Euro-Par.

Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor

Nader Bagherzadeh, Steven Wallace, Nirav Dagli, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs

Masoumeh Ebrahimi, Nader Bagherzadeh, Misagh Khayambashi, 2016, IEEE Transactions on Computers.

A 20 MHz CMOS reorder buffer for a superscalar microprocessor

Nader Bagherzadeh, John Lenell, Steve Wallace, 1992 .

Low power data prefetch for 3D image applications on coarse-grain reconfigurable architectures

Román Hermida, Nader Bagherzadeh, Marcos Sanchez-Elez, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Mobile Agents for Wireless Sensor Networks

Theo Ungerer, Nader Bagherzadeh, Faruk Bagci, 2009, ICWN.

Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC

Nader Bagherzadeh, Pooria M. Yaghini, Ashkan Eghbal, 2015, NOCS.

A Radiation Hard Sense Circuit for Spin Transfer Torque Random Access Memory

Masoomeh Jasemi, Michael M. Green, Nader Bagherzadeh, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks

Theo Ungerer, Nader Bagherzadeh, Faruk Bagci, 2008, ICWN.

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh, 2012, Microprocess. Microsystems.

Interactive Ray Tracing on Reconfigurable SIMD Morphosys

Nozar Tabrizi, Manuel Lois Anido, Nader Bagherzadeh, 2003, Embedded Software for SoC.

The MorphoSys dynamically reconfigurable system-on-chip

Fadi J. Kurdahi, Guangming Lu, Nader Bagherzadeh, 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

A General Fault-Tolerant Minimal Routing for Mesh Architectures

Jie Wu, Nader Bagherzadeh, Hongzhi Zhao, 2017, IEEE Transactions on Computers.

Pipelining and bypassing in a VLIW processor

Nader Bagherzadeh, Arthur Abnous, 1992, ISCA.

A performance comparison of several superscalar processor models with a VLIW processor

Nader Bagherzadeh, John Lenell, 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.

A scalable register file architecture for superscalar processors

Nader Bagherzadeh, Steven Wallace, 1998, Microprocess. Microsystems.

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Ali Ahmadinia, Nader Bagherzadeh, Michael Opoku Agyeman, 2018, J. Syst. Archit..

Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform

Nader Bagherzadeh, Amir Hosein Kamalizad, Chengzhi Pan, 2004, IEEE International SOC Conference, 2004. Proceedings..

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

Román Hermida, Nader Bagherzadeh, Marcos Sanchez-Elez, 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

Persepolis: Recovering history with a handheld camera

Nader Bagherzadeh, Antonio Susín, Miguel Sainz, 2003, Eurographics.

Performance analysis and design methodology for a scalable superscalar architecture

Tetsuo Ono, Nader Bagherzadeh, T. Kaio, 1992, MICRO 1992.

Fast Parallel Computation Of Multibody Dynamics

Amir Fijany, Nader Bagherzadeh, Gregory L. Kwan, 1996 .

Online monitoring and adaptive routing for aging mitigation in NoCs

Nader Bagherzadeh, Zana Ghaderi, Ayed Alqahtani, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic

Keivan Navi, Masoomeh Jasemi, Nader Bagherzadeh, 2015, IET Circuits Devices Syst..

Design of a router for network-on-chip

Seung Eun Lee, Nader Bagherzadeh, Jun Ho Bahn, 2007, Int. J. High Perform. Syst. Archit..

Clock Boosting Router: Increasing the Performance of an Adaptive Router in Network-on-Chip (NoC)

Nader Bagherzadeh, S E Lee, 2008 .

Kernel scheduling in reconfigurable computing

Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh, 1999, DATE '99.

CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture

Ayhan Demiriz, Nader Bagherzadeh, Abdulaziz Alhussien, 2013, 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Designing quantum-dot cellular automata counters with energy consumption analysis

Keivan Navi, Nader Bagherzadeh, Mohammad Hossein Moaiyeri, 2015, Microprocess. Microsystems.

Energy efficient hybrid full adder design for digital signal processing in nanoelectronics

Keivan Navi, Fazel Sharifi, Nader Bagherzadeh, 2021, Analog Integrated Circuits and Signal Processing.

Data scheduling and placement in deep learning accelerator

Ahmad Khademzadeh, Nader Bagherzadeh, Seyedeh Yasaman Hosseini Mirmahaleh, 2021, Clust. Comput..

Near Volatile and Non-Volatile Memory Processing in 3D Systems

Masoumeh Ebrahimi, Nader Bagherzadeh, Pooria M. Yaghini, 2021, IEEE Transactions on Emerging Topics in Computing.

Predicting hypotension in the ICU using noninvasive physiological signals

Nader Bagherzadeh, Ehsan Masoumi Khalil Abad, Mina Chookhachizadeh Moghadam, 2020, Comput. Biol. Medicine.

Application Characterization for Near Memory Processing

Masoumeh Ebrahimi, Nader Bagherzadeh, Pooria M. Yaghini, 2021, 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP).

PLAM: A Posit Logarithm-Approximate Multiplier

Nader Bagherzadeh, Guillermo Botella, Min Soo Kim, 2021, IEEE Transactions on Emerging Topics in Computing.

PLAM: a Posit Logarithm-Approximate Multiplier for Power Efficient Posit-based DNNs pdf

Nader Bagherzadeh, Guillermo Botella Juan, Min Soo Kim, 2021, ArXiv.

Moment algorithms for blood vessel detection in infrared images of laser-heated skin

Nader Bagherzadeh, S. Shoari, T. E. Milner, 1997 .

A novel low power Exclusive-OR via cell level-based design function in quantum cellular automata

Keivan Navi, Nader Bagherzadeh, Somaye Mohammadyan, 2017 .

A 3D universal structure based on molecular-QCA and CNT technologies

Keivan Navi, Nader Bagherzadeh, Milad Bagherian Khosroshahy, 2016 .

MorphoSys : An Integrated Reconfigurable Architecture

Nader Bagherzadeh, Hartej Singh, N. Bagherzadeh, 2000 .