A. Arun Goud

Sub-10 nm FinFETs and tunnel-FETs: From devices to systems

Kaushik Roy, Ankit Sharma, A. Arun Goud, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Asymmetric underlapped FinFET based robust SRAM design at 7nm node

Kaushik Roy, Anand Raghunathan, Rangharajan Venkatesan, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Kaushik Roy, Anand Raghunathan, Rangharajan Venkatesan, 2016, ACM J. Emerg. Technol. Comput. Syst..

P-channel Tunneling Field Effect Transistor (TFET): Sub-10nm technology enablement by GaSb-InAs with doped source underlap

Kaushik Roy, A. Arun Goud, Ankit Sharma, 2015, 2015 73rd Annual Device Research Conference (DRC).

Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs

Kaushik Roy, Sri Harsha Choday, A. Arun Goud, 2013, 71st Device Research Conference.