Bharat L. Bhuva

Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

P. Eaton, J. Ahlbin, L. Massengill, 2009, IEEE Transactions on Nuclear Science.

Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process

B.L. Bhuva, J.D. Black, O.A. Amusan, 2008, 2008 IEEE International Reliability Physics Symposium.

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

T. D. Loveless, L. Massengill, B. Bhuva, 2011, IEEE Transactions on Nuclear Science.

Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

W. T. Holman, B L Bhuva, W T Holman, 2011, IEEE Transactions on Nuclear Science.

Quantifying the Effect of Guard Rings and Guard Drains in Mitigating Charge Collection and Charge Spread

B. Narasimham, B.L. Bhuva, L.W. Massengill, 2008, IEEE Transactions on Nuclear Science.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

A.F. Witulski, L.W. Massengill, B.L. Bhuva, 2007, IEEE Transactions on Nuclear Science.