Jhong-Yu Wang

A 3.1 Gb/s 8 $\,\times\,$ 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition

Yuan-Hao Huang, Chun-Fu Liao, Jhong-Yu Wang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 0.18nJ/Matrix QR decomposition and lattice reduction processor for 8×8 MIMO preprocessing

Yuan-Hao Huang, Chun-Fu Liao, Jhong-Yu Wang, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).