J. Kedzierski

发表

Device and substrate design for sub-10 nm MOSFETs

Min Yang, Bruce B. Doris, Meikei Ieong, 2004 .

Jeffrey Bokor, Leland Chang, N. Lindert, 2003 .

Moores law lives on - Ultra-thin body SOI and FinFET CMOS transistors look to continue Moores law for many years to come

Jeffrey Bokor, Jeffrey Bokor, Leland Chang, 2003 .

Novel method for silicon quantum wire transistor fabrication

Jeffrey Bokor, Erik H. Anderson, J. Kedzierski, 1999 .

Extension and source/drain design for high-performance FinFET devices

Ying Zhang, David M. Fried, Meikei Ieong, 2003 .

Epitaxial Graphene Transistors on SiC Substrates

C. Keast, J. Kedzierski, Pei-Lan Hsu, 2008, IEEE Transactions on Electron Devices.

FinFET design considerations based on 3-D simulation and analytical modeling

G. Pei, Edwin C. Kan, P. Oldiges, 2002 .

Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)

M. Ieong, W. Haensch, J. Kedzierski, 2003, IEEE International Electron Devices Meeting 2003.

Ultra-thin Silicon Channel Single- and Double-gate MOSFETs

Bruce B. Doris, Meikei Ieong, J. Kedzierski, 2002 .

Quantum-based Simulation analysis of scaling in ultrathin body device structures

J. Kedzierski, A. Kumar, S. Laux, 2005, IEEE Transactions on Electron Devices.

Issues in NiSi-gated FDSOI device integration

Ying Zhang, M. Steen, Meikei Ieong, 2003, IEEE International Electron Devices Meeting 2003.

Demonstration of FinFET CMOS circuits

J. Kedzierski, E. Nowak, J. Kedzierski, 2002, 60th DRC. Conference Digest Device Research Conference.

Graphene-on-Insulator Transistors Made Using C on Ni Chemical-Vapor Deposition

Jing Kong, C. Keast, J. Kedzierski, 2009, IEEE Electron Device Letters.

Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation

Jeffrey Bokor, Christian Kisielowski, J. Kedzierski, 1997 .

FDSOI Process Technology for Subthreshold-Operation Ultra-Low-Power Electronics

Nisha Checka, J. Kedzierski, Peter W. Wyatt, 2011 .

Sub-50nm FinFET : PMOS

Vivek Subramanian, Jeffrey Bokor, Chenming Hu, 1999 .

Moore's law lives on

Jeffrey Bokor, Chenming Hu, Leland Chang, 2003 .

Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel

J. Bokor, Chenming Hu, V. Subramanian, 2000, IEEE Electron Device Letters.

Channel engineering of SOI MOSFETs for RF applications

C. L. Keast, P. W. Wyatt, J. Kedzierski, 2009, 2009 IEEE International SOI Conference.

Fabrication of metal gated FinFETs through complete gate silicidation with Ni

H.-S.P. Wong, T. Kanarsky, J. Kedzierski, 2004, IEEE Transactions on Electron Devices.

Scaling beyond conventional CMOS device

Meikei Ieong, Ken Rim, J. Kedzierski, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

60 nm planarized ultra-thin body solid phase epitaxy MOSFETs

Jeffrey Bokor, Chenming Hu, Tsu-Jae King, 2000, 58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526).

A functional FinFET-DGCMOS SRAM cell

J. Kedzierski, M. Breitwisch, M. Breitwisch, 2002, Digest. International Electron Devices Meeting,.

A Fin-type independent-double-gate NFET

J. Kedzierski, E. Nowak, J. Kedzierski, 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Vivek Subramanian, Jeffrey Bokor, Chenming Hu, 2002 .