P. Landman

A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

K. Lewis, S. Johansson, B. Parthasarathy, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

Lin Wu, Wai Lee, V. Gupta, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Compact inverse discrete cosine transform circuit for MPEG video decoding

P. Landman, C.-Yu. Hung, 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

V. Gupta, R. Gu, B. Parthasarathy, 2005, IEEE Journal of Solid-State Circuits.

A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

Lin Wu, Wai Lee, Song Wu, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Programmable termination for CML I/O's in high speed CMOS transceivers

V. Gupta, R. Gu, B. Parthasarathy, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).