Yasuo Sato

发表

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test

Yukiya Miura, Yousuke Miyake, Seiji Kajihara, 2014, 2014 IEEE 23rd Asian Test Symposium.

Delay Test Methods For Logic Circuits

Seiji Kajihara, Yasuo Sato, 2008 .

A persistent diagnostic technique for unstable defects

Masahiro Takakura, Yasuo Sato, Iwao Yamazaki, 2002, Proceedings. International Test Conference.

Test generation for multiple-threshold gate-delay fault model

Kazumi Hatayama, Michinobu Nakao, Yasuo Sato, 2001, Proceedings 10th Asian Test Symposium.

Variations in Device Characteristics

Koji Nii, Hidetoshi Onodera, Toshinori Sato, 2019 .

Quality evaluation of pseudorandom patterns of a logic BIST

Michinobu Nakao, Yasuo Sato, 2006 .

A Scan-Out Power Reduction Method for Multi-cycle BIST

Kohei Miyase, Seiji Kajihara, Yasuo Sato, 2012, 2012 IEEE 21st Asian Test Symposium.

ACTUAL STATE AND SUPPRESSION OF A LATERAL FORCE INDUCED AT GUARD RAIL IN RAILWAY TURNOUT

Yasuo Sato, Yoshihiko Sato, Shigeru Miura, 1988 .

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)

Satoshi Fukumoto, Kazumi Hatayama, Kazuhiko Iwasaki, 2002 .

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

Xiaoqing Wen, Seiji Kajihara, Yasuo Sato, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Automatic recognition of spoken words from a large vocabulary using syllable templates

Keikichi Hirose, Tomohiro Inoue, Yasuo Sato, 1984, ICASSP.

Spectral envelope sampling and interpolation in linear predictive analysis of speech

Hynek Hermansky, Yasuo Sato, Hiroya Fujisaki, 1984, ICASSP.

Scan-Out Power Reduction for Logic BIST

Kohei Miyase, Seiji Kajihara, Yasuo Sato, 2013, IEICE Trans. Inf. Syst..

A Framework of High-quality Transition Fault ATPG for Scan Circuits

Xiaoqing Wen, Toshiyuki Maeda, Seiji Kajihara, 2006, 2006 IEEE International Test Conference.

Introduction and Evaluation of Intelligent Parking System Utilizing DSRC In Toyota City

Yasuo Sato, Daisuke Sugie, 2005 .

DART: Dependable VLSI test architecture and its implementation

Motoyuki Sato, Kotaro Shimamura, Kazumi Hatayama, 2012, 2012 IEEE International Test Conference.

Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2016, 2016 21th IEEE European Test Symposium (ETS).

Circuit Failure Prediction by Field Test - A New Task of Testing

Yasuo Sato, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Special session: Multifaceted approaches for field reliability

Yasuo Sato, 2011, 29th VLSI Test Symposium.

On calculation of delay range in fault simulation for test cubes

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Aging test strategy and adaptive test scheduling for SoC failure prediction

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

On estimation of NBTI-Induced delay degradation

Xiaoqing Wen, Kohei Miyase, Yukiya Miura, 2010, 2010 15th IEEE European Test Symposium.

A Statistical Quality Model for Delay Testing

Toshiyuki Maeda, Seiji Kajihara, Yasuo Sato, 2006, IEICE Trans. Electron..

On the effects of real time and contiguous measurement with a digital temperature and voltage sensor

Yousuke Miyake, Seiji Kajihara, Yasuo Sato, 2017, 2017 International Test Conference in Asia (ITC-Asia).

On test pattern compaction with multi-cycle and multi-observation scan test

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, 2010, 2010 10th International Symposium on Communications and Information Technologies.

Timing- and constraint-oriented placement for interconnected LSIs in mainframe design

Reiji Toyoshima, Yasuo Sato, Tatsuki Ishii, 1991, 28th ACM/IEEE Design Automation Conference.

Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip

Hiroshi Takahashi, Seiji Kajihara, Yasuo Sato, 2015, J. Low Power Electron..

Deterministic Built-in Test for Logic Circuits Having Multiple Clocks

Satoshi Fukumoto, Kazumi Hatayama, Kazuhiko Iwasaki, 2003 .

On-chip temperature and voltage measurement for field testing

Yukiya Miura, Yousuke Miyake, Seiji Kajihara, 2012, 2012 17th IEEE European Test Symposium (ETS).

On Delay Test Quality for Test Cubes (IPSJ Transactions on System LSI Design Methodology Vol.3)

Seiji Kajihara, Yasuo Sato, Shinji Oku, 2010 .

Système de commande de système de puissance et dispositif de commande répartie utilisé dans ledit système

Yasuo Sato, Masahiro Watanabe, Shota Omi, 2013 .

Invisible delay quality - SDQM model lights up what could not be seen

Toshiyuki Maeda, Seiji Kajihara, Yasuo Sato, 2005, IEEE International Conference on Test, 2005..

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2016, IEICE Trans. Inf. Syst..

Time-Dependent Degradation in Device Characteristics and Countermeasures by Design

Masahiko Yoshimoto, Masanori Hashimoto, Shuhei Tanakamaru, 2018, VLSI Design and Test for Systems Dependability.

DFT Timing Design Methodology for Logic BIST

Motoyuki Sato, Yasuo Sato, Kazumi Hatayama, 2003 .

Telephone terminal with data processing device and system for supporting a communication

Yasuo Sato, Tomoyoshi Takebayashi, Jun Kakuta, 1998 .

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2015, 2015 20th IEEE European Test Symposium (ETS).

Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC

Michiko Inoue, Yasuo Sato, Gian Mayuga, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Application of high-quality built-in test to industrial designs

Kazumi Hatayama, Michinobu Nakao, Yasuo Sato, 2002, Proceedings. International Test Conference.

An evaluation of defect-oriented test: WELL-controlled low voltage test

Yasuo Sato, Masaki Kohno, Iwao Yamazaki, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

DFT timing design methodology for at-speed BIST

Motoyuki Sato, Kazumi Hatayama, Yasuo Sato, 2003, ASP-DAC '03.

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Mark Mohammad Tehranipoor, Seiji Kajihara, Laung-Terng Wang, 2013, 2013 22nd Asian Test Symposium.

A practical logic BIST for ASIC designs

Motoyuki Sato, Yasuo Sato, Toyohito Ikeya, 2001, Proceedings 10th Asian Test Symposium.

Evaluation of the statistical delay quality model

Toshiyuki Maeda, Seiji Kajihara, Yasuo Sato, 2005, ASP-DAC.

Formulation of the Process of Coarticulation in Terms of Formant Frequencies and Its Application to Automatic Speech Recognition

Hiroya Fujisaki, Yasuo Sato, H. Fujisaki, 1978 .

Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration

Masahiro Takakura, Kazuhiko Iwasaki, Yasuo Sato, 2004, IEICE Trans. Inf. Syst..

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST

Seiji Kajihara, Yasuo Sato, Takaaki Kato, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

Four-Channel Digital Mixer/Equalizer for Mastering

Yasuo Sato, Toshinori Mori, Takashi Matsushige, 1985 .

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, 2013, 2013 22nd Asian Test Symposium.

Automatic Recognition of Semivowels in Spoken Words

Hiroya Fujisaki, Yasuo Sato, Yoshiro Noguchi, 1975 .

Multi Dimensional Display from a sequence MRI data

Yasuo Sato, Hideki shimizu, 1997 .

A BIST approach for very deep sub-micron (VDSM) defects

Michinobu Nakao, Yasuo Sato, Takaharu Nagumo, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

System zur regelung eines leistungssystems und verteilte steuereinrichtung dafür

Yasuo Sato, Masahiro Watanabe, Shota Omi, 2013 .

Visualization technologies for alcohol fueled engine.

Yasuo Sato, Akinori Saito, Hiromichi Yanagihara, 1989 .

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

Xiaoqing Wen, Seiji Kajihara, Yasuo Sato, 2020, IEEE Transactions on Emerging Topics in Computing.

Effective Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Processing device for image data conversion

Satoshi Nakamura, Yasuo Sato, Chiaki Ito, 1993 .

Path delay test compaction with process variation tolerance

Xiaoqing Wen, Toshiyuki Maeda, Seiji Kajihara, 2005, Proceedings. 42nd Design Automation Conference, 2005..

The Energy Management Support System of the Building Group which Utilized IT

Yasuo Sato, Junichiro Eguchi, 2006 .

Temperature-Variation-Aware Test Pattern Optimization

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2011, 2011 Sixteenth IEEE European Test Symposium.

A snapshot algorithm for distributed mobile systems

Toshimitsu Masuzawa, Hideo Fujiwara, Michiko Inoue, 1996, Proceedings of 16th International Conference on Distributed Computing Systems.

FATIGUE TEST RESULTS OF NARROW-GAUGE LINE VEHICLE AXLES AND RECONSIDERATION OF THEIR INSPECTION SYSTEM

Yasuo Sato, Hiromichi Ishiduka, Hiromi Motomatsu, 2001 .

CyberRail: An Enhanced Railway System for Intermodal Transportation

Ryuji Tsuchiya, Yasuo Sato, Kiyotaka Seki, 2001 .

System to support communication

Yasuo Sato, Tomoyoshi Takebayashi, Jun Kakuta, 1998 .

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA

Yousuke Miyake, Seiji Kajihara, Yasuo Sato, 2014, 2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing.

Low Power BIST for Scan-Shift and Capture Power

Kohei Miyase, Seiji Kajihara, Yasuo Sato, 2012, 2012 IEEE 21st Asian Test Symposium.

Genetic algorithm based approach for segmented testing

Sudhakar M. Reddy, Seiji Kajihara, Yasuo Sato, 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W).

New pyrazolylthiolophosphorsaeureester and -thionothiolophosphorsaeureester

Yasuo Sato, Yoshiyuku Okada, 1979 .

Analysis and synthesis of speech based on spectral transform linear predictive method

Hynek Hermansky, Yasuo Sato, Hiroya Fujisaki, 1983, ICASSP.

On Delay Test Quality for Test Cubes

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

A dynamic test compaction procedure for high-quality path delay testing

Xiaoqing Wen, Toshiyuki Maeda, Seiji Kajihara, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A circuit failure prediction mechanism (DART) for high field reliability

Tomokazu Yoneda, Yukiya Miura, Satoshi Ohtake, 2009, 2009 IEEE 8th International Conference on ASIC.

Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2008, IEICE Trans. Inf. Syst..

A Failure Prediction Strategy for Transistor Aging

Hideo Fujiwara, Tomokazu Yoneda, Michiko Inoue, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Recognition of Sensitized Longest Paths in Transition Delay Test

Toshiyuki Maeda, Yasuo Sato, Shuji Hamada, 2006, 2006 IEEE International Test Conference.

Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor

Yukiya Miura, Yousuke Miyake, Seiji Kajihara, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reliability of ECC-based Memory Architectures with Online Self-repair Capabilities (ディペンダブルコンピューティング)

Tomokazu Yoneda, Michiko Inoue, Yuta Yamato, 2014 .

An On-Chip Digital Environment Monitor for Field Test

Yukiya Miura, Yousuke Miyake, Seiji Kajihara, 2014, 2014 IEEE 23rd Asian Test Symposium.

An approach to improve the resolution of defect-based diagnosis

Masahiro Takakura, Yasuo Sato, Iwao Yamazaki, 2001, Proceedings 10th Asian Test Symposium.

Multi-cycle Test with Partial Observation on Scan-Based BIST Structure

Seiji Kajihara, Yasuo Sato, Makoto Matsuzono, 2011, 2011 Asian Test Symposium.

At-speed built-in test for logic circuits with multiple clocks

Yasuo Sato, M. Nakao, K. Hatayama, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Good Die Prediction Modelling from Limited Test Items

Yoshiyuki Nakamura, Seiji Kajihara, Yasuo Sato, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).