Jingjian Zhang

A 25–28Gb/s PLL-based full-rate reference-less CDR in 0.13μm SiGe BiCMOS

Yi Zhang, Xincun Ji, Peng Zhang, 2017, 2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM).

A Wide-gain-range Intermediate Frequency Integrated Circuit for a Superheterodyne Receiver

Sung Min Park, Ying Zhang, Yi Zhang, 2018 .

A monolithic CMOS IF integrated circuit for a superheterodyne transceiver

Xincun Ji, Yi Zhang, Changchun Zhang, 2017, 2017 IEEE 17th International Conference on Ubiquitous Wireless Broadband (ICUWB).