Carsten Bieser

Konzept einer bibliotheksbasiert konfigurierbaren Hardware-Testeinrichtung für eingebettete elektronische Systeme

Carsten Bieser, 2007 .

Hardware/software co-training by FPGA/ASIC synthesis and programming of a RISC microprocessor-core

Klaus D. Müller-Glaser, Jürgen Becker, Jens E. Becker, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup

Klaus D. Müller-Glaser, Matthias Heinz, Carsten Bieser, 2006, 2006 International Conference on Field Programmable Logic and Applications.

A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment

Carsten Bieser, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs

Klaus D. Müller-Glaser, Carsten Bieser, K. Müller-Glaser, 2006, Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06).

Hardware/software co-training lab: from VHDL bit-level coding up to CASE-Tool based system modeling

Klaus D. Müller-Glaser, Jürgen Becker, Carsten Bieser, 2005, 2005 IEEE International Conference on Microelectronic Systems Education (MSE'05).