Stephen W. Keckler

发表

A patch memory system for image processing and computer vision

Chih-Chi Cheng, Jason Clemons, Iuri Frosio, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

Norman P. Jouppi, Doug Burger, Stephen W. Keckler, 2002, ISCA.

Static energy reduction techniques for microprocessor caches

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements

Lorenzo Alvisi, Doug Burger, Stephen W. Keckler, 2002 .

Massively Multithreaded Computing Systems

Stephen W. Keckler, Steven K. Reinhardt, S. Keckler, 2012, Computer.

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

Kathryn S. McKinley, Calvin Lin, Doug Burger, 2004, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004..

Exploiting microarchitectural redundancy for defect tolerance

Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, 2003, Proceedings 21st International Conference on Computer Design.

Measuring Experimental Error in Microprocessor Simulation

Stephen W. Keckler, Doug Burger, Rajagopalan Desikan, 2001, ISCA.

Increasing Interconnection Network Throughput with Virtual Channels

Stephen W. Keckler, 2015, Computer.

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

Errata on "Measuring Experimental Error in Microprocessor Simulation"

Mateo Valero, Doug Burger, Stephen W. Keckler, 2002, CARN.

Fault Aware Instruction Placement for Static Architectures

Calvin Lin, Stephen W. Keckler, Premkishore Shivakumar, 2005 .

A design space evaluation of grid processor architectures

Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler, 2001, MICRO.

TRIPS Application Binary Interface (ABI) Manual

Kathryn S. McKinley, Doug Burger, Stephen W. Keckler, 2005 .

Chapter 2 On-Chip Networks for Multicore Systems

Sriram R. Vangal, Li-Shiuan Peh, Stephen W. Keckler, 2017 .

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture

Jaehyuk Huh, Karthikeyan Sankaralingam, Doug Burger, 2003, IEEE Micro.

Appears in the 2006 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2006) Critical Path Analysis of the TRIPS Architecture

Xia Chen, Doug Burger, Stephen W. Keckler, 2006 .

Segment gating for static energy reduction in networks-on-chip

Stephen W. Keckler, Kyle C. Hale, Boris Grot, 2009, 2009 2nd International Workshop on Network on Chip Architectures.

Multicore Processors and Systems

Kunle Olukotun, H. Peter Hofstee, Stephen W. Keckler, 2009, Integrated Circuits and Systems.

Virtualizing Deep Neural Networks for Memory-Efficient Neural Network Design pdf

Natalia Gimelshein, Jason Clemons, Stephen W. Keckler, 2016, ArXiv.

High performance dense linear algebra on a spatially distributed processor

Robert A. van de Geijn, Jeffrey R. Diamond, Doug Burger, 2008, PPoPP.

Characterizing the SPHINX Speech Recognition System

Doug Burger, Stephen W. Keckler, Kartik K. Agaram, 2001 .

A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior

David A. Wood, Stephen W. Keckler, Joel Hestness, 2014, 2014 IEEE International Symposium on Workload Characterization (IISWC).

Exploiting criticality to reduce bottlenecks in distributed uniprocessors

Doug Burger, Stephen W. Keckler, Madhu Saravana Sibi Govindan, 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

End-to-end validation of architectural power models

Doug Burger, Stephen W. Keckler, Madhu Saravana Sibi Govindan, 2009, ISLPED.

The M-machine multicomputer

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1997, Proceedings of the 28th Annual International Symposium on Microarchitecture.

Scalable selective re-execution for EDGE architectures

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2004, ASPLOS XI.

Anatomy of GPU Memory System for Multi-Application Execution

Mahmut T. Kandemir, Chita R. Das, Stephen W. Keckler, 2015, MEMSYS.

Toggle-Aware Compression for GPUs

Onur Mutlu, Todd C. Mowry, Gennady Pekhimenko, 2015, IEEE Computer Architecture Letters.

Hardware support for fast capability-based addressing

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1994, ASPLOS VI.

Routed inter-ALU networks for ILP scalability and performance

Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler, 2003, Proceedings 21st International Conference on Computer Design.

A compile-time managed multi-level register file hierarchy

William J. Dally, Stephen W. Keckler, Mark Gebhart, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Timeloop: A Systematic Approach to DNN Accelerator Evaluation

Brucek Khailany, Stephen W. Keckler, Joel S. Emer, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Critical path analysis of the TRIPS architecture

Xia Chen, Doug Burger, Stephen W. Keckler, 2006, 2006 IEEE International Symposium on Performance Analysis of Systems and Software.

Assessment of MRAM Technology Characteristics and Architectures

Doug Burger, Stephen W. Keckler, Rajagopalan Desikan, 2001 .

Universal mechanisms for data-parallel architectures

Karthikeyan Sankaralingam, Stephen W. Keckler, Doug Burger, 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

On-Chip Networks for Multicore Systems

Li-Shiuan Peh, Sriram Vangal, Stephen W. Keckler, 2009, Multicore Processors and Systems.

Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems

William J. Dally, Aditya Agrawal, Stephen W. Keckler, 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications

Brucek Khailany, Jason Clemons, Iuri Frosio, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

The TRIPS OPN: A Processor Integrated NoC for Operand Bypass

Stephen W. Keckler, Paul V. Gratz, 2010 .

M-Machine Microarchitecture v1.1

Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee, 1993 .

SimpleScalar Simulation of the PowerPC Instruction Set Architecture

Karthikeyan Sankaralingam, Stephen W. Keckler, Doug Burger, 2001 .

Software Infrastructure and Tools for the TRIPS Prototype

Karthikeyan Sankaralingam, Aaron Smith, Kathryn S. McKinley, 2007 .

Charles R. (Chuck) Moore (1961 - 2012)

Stephen W. Keckler, Doug Burger, Mark Papermaster, 2012, IEEE Micro.

Dataflow Predication

Karthikeyan Sankaralingam, Aaron Smith, Kathryn S. McKinley, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Universal Mechanisms for Data-Parallel Architectures

Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler, 2003, MICRO.

Research Challenges for On-Chip Interconnection Networks

William J. Dally, John D. Owens, Ron Ho, 2007, IEEE Micro.

A Temperature-Aware Power Estimation Methodology

Sani R. Nassif, Emrah Acar, Stephen W. Keckler, 2008 .

Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches

Changkyu Kim, Stephen W. Keckler, Doug Burger, 2003, IEEE Micro.

SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection

Stephen W. Keckler, Brian Zimmer, Michael B. Sullivan, 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

On-Chip Interconnection Networks of the TRIPS Chip

Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler, 2007, IEEE Micro.

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

William J. Dally, Brucek Khailany, Stephen W. Keckler, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications

Mahmut T. Kandemir, Chita R. Das, Stephen W. Keckler, 2014, GPGPU@ASPLOS.

Flexible software profiling of GPU architectures

David W. Nellans, Daniel R. Johnson, Stephen W. Keckler, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

The M-Machine multicomputer

Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee, 1995, MICRO 1995.

Method, system and medium for providing a distributed maschinenverarbeitbares predicate prediction

Stephen W. Keckler, Hadi Esmaeilzadeh, Doug Burger, 2010 .

A NUCA substrate for flexible CMP cache sharing

Jaehyuk Huh, Lixin Zhang, Doug Burger, 2005, ICS.

Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training pdf

Yuan Xie, Jason Clemons, Stephen W. Keckler, 2018, ArXiv.

CLARA: Circular Linked-List Auto and Self Refresh Architecture

Aditya Agrawal, Stephen W. Keckler, Niladrish Chatterjee, 2016, MEMSYS.

Arbitrary Modulus Indexing

Jeffrey R. Diamond, Donald S. Fussell, Stephen W. Keckler, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Realistic Workload Characterization and Analysis for Networks-on-Chip Design

Stephen W. Keckler, Paul V. Gratz, S. Keckler, 2009 .

Kayotee: A Fault Injection-based System to Assess the Safety and Reliability of Autonomous Vehicles to Faults and Errors pdf

Ravishankar K. Iyer, Stephen W. Keckler, Zbigniew Kalbarczyk, 2019, ArXiv.

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

Onur Mutlu, Stephen W. Keckler, Gwangsun Kim, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

21st century digital design tools

William J. Dally, Stephen W. Keckler, Chris Malachowsky, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Polymorphous architectures: a unified approach for extracting concurrency of different granularities

Karthikeyan Sankaralingam, Stephen W. Keckler, S. Keckler, 2006 .

Regional congestion awareness for load balance in networks-on-chip

Stephen W. Keckler, Paul Gratz, Boris Grot, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

GPUs and the Future of Parallel Computing

William J. Dally, Michael Garland, David Glasco, 2011, IEEE Micro.

Reconciling performance and programmability in networking systems

Harrick M. Vin, Stephen W. Keckler, Jayaram Mudigonda, 2007, SIGCOMM '07.

Multitasking workload scheduling on flexible core chip multiprocessors

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2008, CARN.

GPU computing and the road to extreme-scale parallel systems

Stephen W. Keckler, 2011, IISWC 2011.

TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP

Jaehyuk Huh, Karthikeyan Sankaralingam, Doug Burger, 2004, TACO.

Reconciling performance and programmability in networking systems

Harrick M. Vin, Stephen W. Keckler, Jayaram Mudigonda, 2007, SIGCOMM 2007.

Topology-Aware quality-of-service support in highly integrated chip multiprocessors

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2010, ISCA'10.

Implementation and Evaluation of On-Chip Network Architectures

Doug Burger, Stephen W. Keckler, Paul Gratz, 2006, 2006 International Conference on Computer Design.

A case for toggle-aware compression for GPU systems

Onur Mutlu, Todd C. Mowry, Gennady Pekhimenko, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

ReFLEX: Block Atomic Execution on Conventional ISA Cores

Stephen W. Keckler, Mark Gebhart, 2010 .

A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2012, IEEE Micro.

Combining Hyperblocks and Exit Prediction to Increase Front-End Bandwidth and Performance

Calvin Lin, Doug Burger, Stephen W. Keckler, 2002 .

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

William J. Dally, Yanqing Zhang, Brucek Khailany, 2019, MICRO.

Scaling the Power Wall: A Path to Exascale

William J. Dally, Justin Luitjens, David W. Nellans, 2014, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis.

Evaluation and optimization of multicore performance bottlenecks in supercomputing applications

James C. Browne, Martin Burtscher, Byoung-Do Kim, 2011, (IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.

Optimizing Software-Directed Instruction Replication for GPU Error Detection

Stephen W. Keckler, Abdulrahman Mahmoud, Michael B. Sullivan, 2018, SC18: International Conference for High Performance Computing, Networking, Storage and Analysis.

Exploiting microarchitectural redundancy for defect tolerance

Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, 2003, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Composable Multicore Chips

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2009, Multicore Processors and Systems.

SCNN: An accelerator for compressed-sparse convolutional neural networks

William J. Dally, Antonio Puglielli, Brucek Khailany, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA

Stephen W. Keckler, Luiz Andre Barroso, 2009, ISCA.

Energy-efficient mechanisms for managing thread context in throughput processors

William J. Dally, Kevin Skadron, Daniel R. Johnson, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Modeling the effect of technology trends on the soft error rate of combinational logic

Lorenzo Alvisi, Doug Burger, Stephen W. Keckler, 2002, Proceedings International Conference on Dependable Systems and Networks.

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

Doug Burger, Stephen W. Keckler, Changkyu Kim, 2002, ASPLOS X.

Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs

David W. Nellans, Mattan Erez, Stephen W. Keckler, 2019, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism

William J. Dally, Stephen W. Keckler, Stephem W. Keckler, 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

Scalable hardware memory disambiguation for high-ILP processors

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2003, IEEE Micro.

Concurrent Event Handling through Multithreading

William J. Dally, Stephen W. Keckler, Sandeep Chatterjee, 1999, IEEE Trans. Computers.

Scaling to the end of silicon with EDGE architectures

Lizy Kurian John, Michael Dahlin, Kathryn S. McKinley, 2004, Computer.

Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs

Stephen W. Keckler, Mark Stephenson, Neal C. Crago, 2018, ACM Trans. Archit. Code Optim..

The future of multi-core technologies

H. Peter Hofstee, Stephen W. Keckler, Ian Buck, 2007, CLUSTER.

Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation

Kathryn S. McKinley, Stephen W. Keckler, Doug Burger, 2008 .

How to implement effective prediction and forwarding for fusable dynamic multicore architectures

Dong Li, Aaron Smith, Doug Burger, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

An evaluation of the TRIPS computer system

Jeffrey R. Diamond, Mario Marino, Aaron Smith, 2009, ASPLOS.

Decomposing memory performance: data structures and phases

Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler, 2006, ISMM '06.

Techniques to improve the hard and soft error reliability of distributed architectures

Stephen W. Keckler, Premkishore Shivakumar, S. Keckler, 2007 .

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Krste Asanovic, Stephen W. Keckler, Ronny Krashinsky, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Fast thread communication and synchronization mechanisms for a scalable single chip multiprocessor

Stephen W. Keckler, S. Keckler, 1998 .

On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories

Doug Burger, Stephen W. Keckler, Rajagopalan Desikan, 2004 .

SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation

Stephen W. Keckler, Mark Stephenson, Joel S. Emer, 2017, 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Estimating Silent Data Corruption Rates Using a Two-Level Model pdf

Joel Emer, Stephen W. Keckler, Paolo Rech, 2020, ArXiv.

An Evaluation of the TRIPS Computer System (Extended Technical Report)

Kathryn S. McKinley, Bertrand A. Maher, Mario Donato Marino, 2008 .

Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

William J. Dally, Stephen W. Keckler, Daniel Maskit, 1998, Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235).

Power, Performance, and Thermal Management for High-Performance Systems

Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Speculative reconvergence for improved SIMT efficiency

Stephen W. Keckler, Olivier Giroux, Eddie Yan, 2020, CGO.

Scalable On-Chip Interconnect Topologies

Stephen W. Keckler, Boris Grot, S. Keckler, 2008 .

Late-binding: enabling unordered load-store queues

Simha Sethumadhavan, Franziska Roesner, Doug Burger, 2007, ISCA '07.

ML-Based Fault Injection for Autonomous Vehicles: A Case for Bayesian Fault Injection

Ravishankar K. Iyer, Zbigniew T. Kalbarczyk, Stephen W. Keckler, 2019, 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

SNAP: A 1.67 — 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS

Chester Liu, Stephen W. Keckler, Zhengya Zhang, 2019, 2019 Symposium on VLSI Circuits.

Network-on-chip implementation and performance improvement through workload characterization and congestion awareness

Stephen W. Keckler, Paul V. Gratz, S. Keckler, 2008 .

Training Long Short-Term Memory With Sparsified Stochastic Gradient Descent

Yuan Xie, Jason Clemons, Stephen W. Keckler, 2017 .

Towards high performance paged memory for GPUs

David W. Nellans, Stephen W. Keckler, Mark Stephenson, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Architecture And Implementation Of The Trips Processor

Simha Sethumadhavan, Karthikeyan Sankaralingam, Stephen W. Keckler, 2007 .

Analysis of the TRIPS prototype block predictor

Doug Burger, Stephen W. Keckler, Nitya Ranganathan, 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

A Coupled Multi-ALU Processing Node for a Highly Parallel Computer

Stephen W. Keckler, 1992 .

HarDNN: Feature Map Vulnerability Evaluation in CNNs pdf

Charbel Sakr, Pavlo Molchanov, Sarita V. Adve, 2020, ArXiv.

Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications

Guanpeng Li, Karthik Pattabiraman, Stephen W. Keckler, 2017, SC17: International Conference for High Performance Computing, Networking, Storage and Analysis.

Unlocking bandwidth for GPUs in CC-NUMA systems

Thomas F. Wenisch, David W. Nellans, Stephen W. Keckler, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Scaling Power and Performance viaProcessor Composability

Dong Li, Aaron Smith, Bertrand A. Maher, 2014, IEEE Transactions on Computers.

2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), 2008

Stephen W. Keckler, Boris Grot, 2008 .

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Simha Sethumadhavan, Karthikeyan Sankaralingam, Doug Burger, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Clock rate versus IPC: the end of the road for conventional microarchitectures

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

An Efficient, Protected Message Interface

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1998, Computer.

Implementation of the Control Unit in the TRIPS Prototype Processor

Doug Burger, Stephen W. Keckler, Ramadass Nagarajan, 2006 .

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration

Jason Clemons, Stephen W. Keckler, Joel S. Emer, 2019, ASPLOS.

GPU snapshot: checkpoint offloading for GPU-dense systems

Mattan Erez, Stephen W. Keckler, Michael B. Sullivan, 2019, ICS.

Selective GPU caches to eliminate CPU-GPU HW cache coherence

Thomas F. Wenisch, David W. Nellans, Stephen W. Keckler, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors

William J. Dally, Kevin Skadron, Daniel R. Johnson, 2012, TOCS.

Recent extensions to the SimpleScalar tool suite

Todd M. Austin, Doug Burger, Stephen W. Keckler, 2004, PERV.

Instruction scheduling for emerging communication-exposed architectures

Kathryn S. McKinley, Stephen W. Keckler, Doug Burger, 2004, PACT 2004.

Rethinking caches for throughput processors: technical perspective

Stephen W. Keckler, 2014, CACM.

A characterization of speech recognition on modern computer systems

Doug Burger, Stephen W. Keckler, Kartik K. Agaram, 2001 .

Counting Dependence Predictors

Franziska Roesner, Doug Burger, Stephen W. Keckler, 2008, 2008 International Symposium on Computer Architecture.

On the Trend of Resilience for GPU-Dense Systems

Mattan Erez, Stephen W. Keckler, Michael B. Sullivan, 2019, 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume (DSN-S).

NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs

Oreste Villa, Stephen W. Keckler, Mark Stephenson, 2019, MICRO.

Design and Implementation of the TRIPS Primary Memory System

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2006, 2006 International Conference on Computer Design.

Preemptive Virtual Clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A NUCA Substrate for Flexible CMP Cache Sharing

Jaehyuk Huh, Lixin Zhang, Doug Burger, 2007, IEEE Transactions on Parallel and Distributed Systems.

GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors

David A. Wood, Stephen W. Keckler, Joel Hestness, 2015, 2015 IEEE International Symposium on Workload Characterization.

Scalable Hardware Memory Disambiguation for High-ILP Processors

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2004, IEEE Micro.

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm

William J. Dally, Brucek Khailany, Stephen G. Tell, 2019, 2019 Symposium on VLSI Circuits.

Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures

Kathryn S. McKinley, Calvin Lin, Doug Burger, 2004, IEEE PACT.

Express Cube Topologies for on-Chip Interconnects

Onur Mutlu, Stephen W. Keckler, Boris Grot, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar

Dean M. Tullsen, Stephen W. Keckler, 2014, IEEE Micro.

vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design

Natalia Gimelshein, Jason Clemons, Stephen W. Keckler, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Implementation and Evaluation of a Dynamically Routed Processor Operand Network

Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler, 2007, First International Symposium on Networks-on-Chip (NOCS'07).

Netrace: dependency-driven trace-based network-on-chip simulation

Stephen W. Keckler, Boris Grot, Joel Hestness, 2010, NoCArc '10.

Microprocessor Pi pel i ne Energy Analysis

Doug Burger, Stephen W. Keckler, Karthik Natarajan, 2003 .

Architecting an Energy-Efficient DRAM System for GPUs

William J. Dally, Daniel R. Johnson, Stephen W. Keckler, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

Stephen W. Keckler, Mark Stephenson, Neha Agarwal, 2015, ASPLOS.

Exploring the design space of future CMPs

Jaehyuk Huh, Doug Burger, Stephen W. Keckler, 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.

The Effect of Technology Scaling on Microarchitectural Structures

Vinod K. Agarwal, Doug Burger, Stephen W. Keckler, 2000 .

Thermal response to DVFS: analysis with an Intel Pentium M

Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Jaehyuk Huh, Karthikeyan Sankaralingam, Doug Burger, 2003, ISCA '03.

TRIPS Intermediate Language (TIL) Manual

Kathryn S. McKinley, Doug Burger, Stephen W. Keckler, 2005 .

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

Onur Mutlu, Stephen W. Keckler, Gwangsun Kim, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

The impact of delay on the design of branch predictors

Daniel A. Jiménez, Calvin Lin, Stephen W. Keckler, 2000, MICRO 33.

Measuring Experimental Error in Microprocessor Simulation

Doug Burger, Stephen W. Keckler, Rajagopalan Desikan, 2001, ISCA 2001.

Tera-Op Reliable Intelligently Adaptive Processing System (TRIPS)

Tom Keller, Kathryn S. McKinley, Calvin Lin, 2004 .

Architecture for High Performance Systems

Vikas Agarwal, Karthikeyan Sankaralingam, Doug Burger, 2003 .

Designing Efficient Heterogeneous Memory Architectures

Alex Ramírez, David W. Nellans, Oreste Villa, 2015, IEEE Micro.

Coordinated power, energy, and temperature management

Stephen W. Keckler, Heather L. Hanson, 2007 .

A variable warp size architecture

Daniel R. Johnson, Stephen W. Keckler, Mike O'Connor, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Static energy reduction techniques for microprocessor caches

Vikas Agarwal, Doug Burger, Stephen W. Keckler, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Software-Directed Techniques for Improved GPU Register File Utilization

Stephen W. Keckler, Mark Stephenson, Arslan Zulfiqar, 2018, ACM Trans. Archit. Code Optim..

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

William J. Dally, Yanqing Zhang, Brucek Khailany, 2020, IEEE Journal of Solid-State Circuits.

Making Convolutions Resilient Via Algorithm-Based Error Detection Techniques pdf

Stephen W. Keckler, Michael B. Sullivan, Timothy Tsai, 2020, IEEE Transactions on Dependable and Secure Computing.

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

Stephen W. Keckler, Niladrish Chatterjee, Mike O'Connor, 2017, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Convergence and scalarization for data-parallel architectures

Krste Asanovic, Stephen W. Keckler, Ronny Krashinsky, 2013, Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO).

A Routing Network for the Grid Processor Architecture

Doug Burger, Stephen W. Keckler, Vincent Ajay Singh, 2003 .

MAGNet: A Modular Accelerator Generator for Neural Networks

William J. Dally, Brucek Khailany, Jason Clemons, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

NVBitFI: Dynamic Fault Injection for GPUs

Stephen W. Keckler, Oreste Villa, Timothy Tsai, 2021, 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

GPU Domain Specialization via Composable On-Package Architecture pdf

David W. Nellans, Stephen W. Keckler, Niladrish Chatterjee, 2021, ACM Trans. Archit. Code Optim..

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

Stephen W. Keckler, Zhengya Zhang, Yakun Sophia Shao, 2021, IEEE Journal of Solid-State Circuits.

Evolution of the Graphics Processing Unit (GPU)

William J. Dally, Stephen W. Keckler, David B. Kirk, 2021, IEEE Micro.

Suraksha: A Quantitative AV Safety Evaluation Framework to Analyze Safety Implications of Perception Design Choices

Stephen W. Keckler, Hengyu Zhao, Timothy Tsai, 2021, 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).

Cooperative Profile Guided Optimizations

Stephen W. Keckler, Ram Rangan, Mark Stephenson, 2021, Comput. Graph. Forum.

Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles

Zahra Ghodsi, Siddharth Garg, Iuri Frosio, 2021, 2021 IEEE Intelligent Vehicles Symposium (IV).

The Mmmachine Multicomputer

William J. Dally, Stephen W. Keckler, Nicholas P. Carter, 1995 .

Measuring the Radiation Reliability of SRAM Structures in GPUs Designed for HPC

Luigi Carro, Stephen W. Keckler, Paolo Rech, 2014 .

Power and Performance Optimization : A Case Study with the Pentium M Processor

Stephen W. Keckler, Heather Hanson, 2006 .

Breaking the GOP / Watt Barrier with EDGE Architectures

Doug Burger, Stephen W. Keckler, 2005 .