R. Gauthier

发表

Failure Analysis of I/O with ESD Protection Devices in Advanced CMOS Technologies

M. Muhammad, R. Gauthier, K. Chatty, 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Transient latch-up of switching arrays in power management circuits

R. Gauthier, N. Peachey, R. Phelps, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection

R. Gauthier, K. Chatty, Junjun Li, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation

R. Gauthier, J. B. Johnson, S. Mitra, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Advanced ESD tool flow, testing and design verification results

M. Muhammad, R. Gauthier, S. Mitra, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Study of gated pnp as an ESD protection device for mixed-voltage and hot-pluggable circuit applications

R. Gauthier, V. Gross, Minh Toug, 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

M. Muhammad, R. Gauthier, K. Chatty, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection

R. Gauthier, E. Rosenbaum, Junjun Li, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies

R. Gauthier, C. Seguin, S. Mitra, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Design and optimization of SCR devices for on-chip ESD protection in advanced SOI CMOS technologies

R. Gauthier, Junjun Li, J. Di Sarro, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness

M. Muhammad, R. Gauthier, K. Chatty, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Evaluation of diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13 µm CMOS logic technology

M. Muhammad, R. Gauthier, C. Putnam, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

TLP systems with combined 50 and 500-ohm impedance probes and kelvin probes

R. Gauthier, E. Grund, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Evaluation of ESD characteristics for 65 nm SOI technology

R. Gauthier, C. Seguin, S. Mitra, 2005, 2005 IEEE International SOI Conference Proceedings.

VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing

R. Gauthier, E. Grund, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Interaction between electrostatic discharge and electromigration on copper interconnects for advanced CMOS technologies

M. Muhammad, R. Gauthier, K. Chatty, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-/spl mu/m CMOS technology

Akram A. Salman, R. Gauthier, Dimitris E. Ioannou, 2002 .

TLP systems with combined 50- and 500-/spl Omega/ impedance probes and Kelvin probes

R. Gauthier, E. Grund, 2005, IEEE Transactions on Electronics Packaging Manufacturing.

Human Body Model ESD protection concepts in SOI and bulk CMOS at the 130 nm node

M. Muhammad, R. Gauthier, K. Chatty, 2003, 2003 IEEE International Conference on SOI.

Effect of embedded-SiGe (eSiGe) on ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers (DTSCRs)

R. Gauthier, Rahul Mishra, Junjun Li, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

ESD protection using grounded gate, gate non-silicided (GG-GNS) ESD NFETs in 45nm SOI technology

R. Gauthier, C. Seguin, S. Mitra, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

M. Muhammad, R. Gauthier, K. Chatty, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

Investigation of ESD performance of silicide-blocked stacked NMOSFETs in a 45nm bulk CMOS technology

R. Gauthier, K. Chatty, C. Russ, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

R. Gauthier, J. Pekarik, J. Pekarik, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

R. Gauthier, K. Chatty, E. Rosenbaum, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

R. Gauthier, K. Chatty, C. Seguin, 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies

R. Gauthier, K. Chatty, C. Russ, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Capacitance investigation of diode and GGNMOS for ESD protection of high frequency circuits in 45nm SOI CMOS technologies

R. Gauthier, K. Chatty, S. Mitra, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

R. Gauthier, K. Chatty, S. Mitra, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

R. Gauthier, S. Mitra, D.E. Ioannou, 2008, IEEE Electron Device Letters.

On The Interaction of ESD, NBTI and HCI in 65nm Technology

R. Gauthier, K. Chatty, C. Seguin, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.