Hironori Nakajo

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Editor's Message to Special Issue on Embedded Systems Engineering

Hironori Nakajo, 2020, J. Inf. Process..

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2005, PDPTA.

Editor's Message to Special Issue on Embedded Systems Engineering

Hironori Nakajo, 2019, J. Inf. Process..

Japanese High-level Synthesis Tools for Fpga Hardware Acceleration *

Minoru Watanabe, Hironori Nakajo, Takefumi Miyoshi, 2016 .

Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot

Hideharu Amano, Noboru Tanabe, Hiroaki Nishi, 2004, Cluster Computing.

Performance evaluation of an SoC for the real-time lens-free imager RALFIE

Hironori Nakajo, Naoya Kitagawa, Kohta Ohshima, 2017, 2017 IEEE 6th Global Conference on Consumer Electronics (GCCE).

Detecting water waste activities for water-efficient living

Juha Röning, Jaakko Suutala, Pekka Siirtola, 2011, UbiComp '11.

Towards Reconfigurable Cache Memory for a Multithreaded Processor

Hironori Nakajo, Mikiko Sato, Satoshi Watanabe, 2006, PDPTA.

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Hiroshi Nakashima, Hideharu Amano, Hideo Matsuda, 1994, Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN).

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot

Hideharu Amano, Noboru Tanabe, Tomohiro Kudoh, 2002, PARELEC.

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2005, ISHPC.

Development of a Thread Scheduler for SMT Processor Architecture

Hironori Nakajo, Mikiko Sato, Mitaro Namiki, 2005, PDPTA.

Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices

Hironori Nakajo, Jingyong Cai, Masashi Takemoto, 2018, 2018 IEEE 7th Global Conference on Consumer Electronics (GCCE).

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation

Hironori Nakajo, Mikiko Sato, Mitaro Namiki, 2005, PDPTA.

A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links

Hironori Nakajo, Yukio Kaneda, Akihiro Ichikawa, 2000, International Journal of Parallel Programming.

Scalable Hardware Mechanism for Partitioned Circuits Operation

Hironori Nakajo, Yusuke Katoh, Hironari Yoshiuchi, 2018 .

Performance Evaluation of Communication with Martini's On -Chip- Processor on DIMMnet - 1

Hideharu Amano, Noboru Tanabe, Tomohiro Kudoh, 2002 .

A memory accelerator with gather functions for bandwidth-bound irregular applications

Masami Takata, Noboru Tanabe, Kazuki Joe, 2011, IA3 '11.

Network Interface Architecture for Scalable Message Queue Processing

Noboru Tanabe, Atsushi Ohta, Hironori Nakajo, 2009, 2009 15th International Conference on Parallel and Distributed Systems.

A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks

Hironori Nakajo, Jingyong Cai, Masashi Takemoto, 2018, IAIT.

The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing

Masami Takata, Noboru Tanabe, Kazuki Joe, 2009, PDPTA.

An Implementation of a Distibuted Image Generation Sistem using Fast Serial Link

Hironori Nakajo, Yukio Kaneda, Masaki Kohata, 1993 .

A New Memory Module for Memory Intensive Applications

Hideharu Amano, Noboru Tanabe, Yasunori Dohi, 2004 .

An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing

Noboru Tanabe, Yasunori Dohi, Hiroshi Ando, 2009, The Journal of Supercomputing.

An architecture of multi-DSP system and development environment for two-dimensional digital signal processing

Hironori Nakajo, T. Hinamoto, K. Yoshikawa, 1992, [Proceedings 1992] IEEE International Conference on Systems Engineering.

Support Functions for MPI on DIMMnet-3 Network Interface

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2006 .

Effects of Conversion of Strided Access into Continuous Access on a Memory Module

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2005 .

Editor's Message to Special Issue on Embedded Systems Engineering

Hironori Nakajo, 2018, J. Inf. Process..

An Effective Replacement Policy Focusing on Lifetime of a Cache Line

Peng Zhang, Hironori Nakajo, Shinobu Miwa, 2010, CDES.

Performance evaluation on low-latency communication mechanism of DIMMnet-2

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2007, Parallel and Distributed Computing and Networks.

Editor's Message to Special Issue on Embedded Systems Engineering

Hironori Nakajo, 2020, J. Inf. Process..

A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture

Hironori Nakajo, Mikiko Sato, Mitaro Namiki, 2003, PDPTA.

Implementation and Evaluation of a Thread Library for Multithreaded Architecture

Hironori Nakajo, Mikiko Sato, Mitaro Namiki, 2003, PDPTA.

Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage

Juha Röning, Jaakko Suutala, Pekka Siirtola, 2011, 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications.

BOTF: A High Bandwidth Communication Mechanism of DIMMnet-1 Network Interface Plugged into a DIMM Slot

Hideharu Amano, Noboru Tanabe, Tomohiro Kudoh, 2002 .

Parallelizing Hilbert-Huang Transform on a GPU

Yasue Mitsukura, Hironori Nakajo, Shinobu Miwa, 2010, 2010 First International Conference on Networking and Computing.

A low latency high bandwidth network interface prototype for PC cluster

Hideharu Amano, Noboru Tanabe, Tomohiro Kudoh, 2002, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.

High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1

Hideo Matsuda, Takashi Matsumoto, Kei Hiraki, 1995, Parallel and Distributed Computing and Systems.

Implementation of PC Cluster System with Memory Mapped File by Commodity OS

Noboru Tanabe, Jun Kanai, Hironori Nakajo, 2006, PDPTA.

Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning

Huynh Thi Thanh Binh, Hironori Nakajo, Tran Van Hoai, 2019, SoICT.

Feasibility of an Embedded Virtual Machine under Parallel or Distributed Processing Environment

Masaki Nakanishi, Hironori Nakajo, Shinobu Miwa, 2009 .

A New Memory Module for Memory Intensive Applications

Hideharu Amano, Noboru Tanabe, Yasunori Dohi, 2004, Parallel Computing in Electrical Engineering, 2004. International Conference on.

MEMOnet: network interface plugged into a memory slot

Noboru Tanabe, Hiroaki Nishi, Tomohiro Kudoh, 2000, Proceedings IEEE International Conference on Cluster Computing. CLUSTER 2000.

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2007, PDPTA.

An I/O network architecture of the distributed shared-memory massively parallel computer JUMP-1

Takashi Matsumoto, Kei Hiraki, Hironori Nakajo, 1997, ICS '97.

Memory Management of Thread Local Memory on a System Software for Multithreaded Architecture OChiMuS PE

Takahiro Shinagawa, Hironori Nakajo, Mikiko Sato, 2007 .

Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices

Hironori Nakajo, Satoshi Watanabe, Yoshiyasu Ogasawara, 2007, PDPTA.

Design of real-time advanced lens free imager

Hironori Nakajo, Naoya Kitagawa, Kohta Ohshima, 2016, SoICT.

Framework for a Hybrid System with a pair of MCU and FPGA

Hironori Nakajo, Suzuki Ryota, 2017 .

Performance evaluation of communication on DIMMnet - 1 network interface plugged into a DIMM slot

Hideharu Amano, Noboru Tanabe, Tomohiro Kudoh, 2001 .

PyJer : A Framework for Prototyping of IoT Devices with High Level Synthesis Tools and SoC

Hironori Nakajo, Daichi Teruya, Daichi Miyazaki, 2017 .

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board

Akira Kitamura, Hideharu Amano, Noboru Tanabe, 2005, Sixth International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'05).

On-the-fly sending: a low latency high bandwidth message transfer mechanism

Hideharu Amano, Noboru Tanabe, Hiroaki Nishi, 2000, Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000.

Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis

Yasue Mitsukura, Hironori Nakajo, Shinobu Miwa, 2011, IEICE Trans. Inf. Syst..

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number

Hironori Nakajo, Mikiko Sato, Mitaro Namiki, 2003, PDPTA.

An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links

Hironori Nakajo, Yukio Kaneda, Akihiro Ichikawa, 1997, ISHPC.

Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph

Keiichi Kaneko, Hironori Nakajo, Yo Nishiyama, 2018, J. Inf. Sci. Eng..

Performance of Parallel Processing of Volume Rendering for Huge Data with Cell/B.E. and DIMMnet

Noboru Tanabe, Kazuki Joe, Hironori Nakajo, 2009 .

Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool

Hironori Nakajo, Takefumi Miyoshi, Yuto Ishikawa, 2017, HEART.

A Model of Implementable SMT Processor on FPGA

Hironori Nakajo, Mikiko Sato, Satoshi Watanabe, 2006, PDPTA.

An Enhancer of Memory and Network for Cluster and its Applications

Noboru Tanabe, Hironori Nakajo, 2008, 2008 Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies.

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor

Hironori Nakajo, Shinobu Miwa, Yoshiyasu Ogasawara, 2009, CDES.

Low-Complexity Bypass Network Using Small RAM

Masahiro Goshima, Hidetsugu Irie, Shinji Tomita, 2008, CDES.

bDais : evaluating a router between the DIMMnet - 1 and the InfiniBand

Hideharu Amano, Noboru Tanabe, Hiroaki Nishi, 2004 .

Acceleration for MPI derived datatypes using an enhancer of memory and network

Noboru Tanabe, Hironori Nakajo, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

A simulation-based evaluation of a disk I/O subsystem for a massively parallel computer: JUMP-1

Hironori Nakajo, Yukio Kaneda, Satoshi Ohtani, 1996, Proceedings of 16th International Conference on Distributed Computing Systems.

An Effective Replacement Strategy of Cache Memory for an SMT Processor

Hironori Nakajo, Yoshiyasu Ogasawara, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot

Akira Kitamura, Noboru Tanabe, Hironori Nakajo, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface

Hidekazu Tanaka, Hironori Nakajo, Yukio Kaneda, 1998, HPCN Europe.

Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network

Noboru Tanabe, Hironori Nakajo, 2008, PVM/MPI.

Coherence Protocol for Home Proxy Cache on RHiNET

Hideharu Amano, Hironori Nakajo, M. Ishii, 2000, PDPTA.

Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor

Hironori Nakajo, Mikiko Sato, Mitaro Namiki, 2004, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04).

Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering

Huynh Thi Thanh Binh, Hironori Nakajo, Masashi Takemoto, 2018, SoICT.

Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices

Atsushi Ohta, Hironori Nakajo, Kaori Fujinami, 2011, 2011 Second International Conference on Networking and Computing.

Editor's Message to Special Issue of Embedded Systems Engineering

Hironori Nakajo, 2021, J. Inf. Process..

Trigonometric Inference Providing Learning in Deep Neural Networks

Hironori Nakajo, Masashi Takemoto, Jingyong Cai, 2021, Applied Sciences.