K. Numata

A 1.6 GB/s data-transfer-rate 8 Mb embedded DRAM

T. Furuyama, T. Yabe, M. Enkaku, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

M. Wada, M. Enkaku, K. Sato, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

Yukihito Oowaki, Shigeyoshi Watanabe, Akihiro Nitayama, 1987 .