J. Sonntag

A monolithic CMOS 10 MHz DPLL for burst-mode data retiming

J. Sonntag, R. Leonowich, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

FA 9.6: A 5.75b 350MSamplels or 6.75b 150MSamplels Reconfigurable Flash ADC for a PRML Read Channel

J. Plany, H. Burger, P. Setty, 1998 .

A 5.75 b 350 M sample/s or 6.75 b 150 M sample/s reconfigurable flash ADC for a PRML read channel

J. Plany, J. Barner, H. Burger, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

Using additive white binary noise to marginalize read channels

N. Sayiner, J. Sonntag, 1998 .

A high speed, low power PRML read channel device

K. Nagaraj, V. Comino, J. M. Khoury, 1995 .

A High Speed, Low Power PRML Read Channel

O. Agazzi, K. Nagaraj, V. Comino, 1994, Digest of the Magnetic Recording Conference.