Sying-Jyan Wang

发表

Optimized Pre-bond Test Methodology for Silicon Interposer Testing

Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, 2014, 2014 IEEE 23rd Asian Test Symposium.

Test Data Compression for Minimum Test Application Time

Ching-Hung Lin, Sying-Jyan Wang, Po-Chang Tsai, 2007, J. Inf. Sci. Eng..

Low-power delay test architecture for pre-bond test

Katherine Shu-Min Li, Sying-Jyan Wang, Han-Hsuan Hsu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Design and synthesis of self-checking VLSI circuits

Niraj K. Jha, Sying-Jyan Wang, N. Jha, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Static and dynamic test power reduction in scan-based testing

Katherine Shu-Min Li, Sying-Jyan Wang, Shun-Jie Huang, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture

Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, 2007, 16th Asian Test Symposium (ATS 2007).

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques

Katherine Shu-Min Li, Sying-Jyan Wang, Peter Yi-Yu Liao, 2020, 2020 IEEE European Test Symposium (ETS).

Test generation for combinational hardware Trojans

Katherine Shu-Min Li, Sying-Jyan Wang, Jhih-Yu Wei, 2016, 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST).

Watermarking for Paper-Based Digital Microfluidic Biochips

Tsung-Yi Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

High-Level Test Synthesis for Delay Fault Testability

Sying-Jyan Wang, Tung-Hua Yeh, Sying-Jyan Wang, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package

Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2013, 2013 22nd Asian Test Symposium.

Layout-aware scan chain reorder for launch-off-shift transition test coverage

Katherine Shu-Min Li, Sying-Jyan Wang, Kuo-Lin Peng, 2008, TODE.

Correction to Algorithm-Based Fault Tolerance for FFT Networks

Sying-Jyan Wang, N. K. Jha, 1994 .

A layout-aware test methodology for silicon interposer in 3D System-in-a-Package

Liang-Bi Chen, Yingchieh Ho, Sying-Jyan Wang, 2013, 2013 International Symposium on Next-Generation Electronics.

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis

Sying-Jyan Wang, Xin-Long Li, K. Shu-Min Li, 2007, 16th Asian Test Symposium (ATS 2007).

Test and diagnosis of faulty logic blocks in FPGAs

Sying-Jyan Wang, Tsi-Ming Tsai, 1997, ICCAD 1997.

Design and analysis of fault-tolerant multistage interconnection networks

Sying-Jyan Wang, Sying-Jyan Wang, 1992 .

Test and diagnosis of paper-based microfluidic biochips

Tsung-Yi Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Multiple input bridging fault detection in CMOS sequential circuits

Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Generating efficient tests for continuous scan

Sying-Jyan Wang, Sheng-Nan Chiou, 2001, DAC '01.

Level converting scan flip-flops

Katherine Shu-Min Li, Sying-Jyan Wang, Ming-Hua Hsieh, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Testing Clock Distribution Networks

Katherine Shu-Min Li, Sying-Jyan Wang, Hsiang-Hsueh Chen, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips

Tsung-Yi Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Exploiting distribution of unknown values in test responses to optimize test output compactors

Katherine Shu-Min Li, Sying-Jyan Wang, Kuan-Ting Yeh, 2019, Integr..

Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage

Katherine Shu-Min Li, Sying-Jyan Wang, Kuo-Lin Peng, 2006, 2006 15th Asian Test Symposium.

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

Sying-Jyan Wang, Tung-Hua Yeh, Sying-Jyan Wang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interconnect test for core-based designs with known circuit characteristics and test patterns

Katherine Shu-Min Li, Sying-Jyan Wang, Tung-Hua Yeh, 2011, 2011 IEEE International Conference on IC Design & Technology.

Thermal Safe High Level Test Synthesis for Hierarchical Testability

Sying-Jyan Wang, Tung-Hua Yeh, Sying-Jyan Wang, 2010, 2010 19th IEEE Asian Test Symposium.

Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches

Sying-Jyan Wang, Chia-Chun Lien, 2000, J. Inf. Sci. Eng..

Adversarial Attack against Modeling Attack on PUFs

Yu-Shen Chen, Katherine Shu-Min Li, Sying-Jyan Wang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Design and Synthesis of Self-Checkmg VLSI Circuits

Niraj K. Jha, Sying-Jyan Wang, 1993 .

De Bruijn graph-based communication modeling for fault tolerance in smart grids

Katherine Shu-Min Li, Sying-Jyan Wang, Bo-Chuan Cheng, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing

Sying-Jyan Wang, 1996, J. Parallel Distributed Comput..

Testing and diagnosis of board interconnects in microprocessor-based systems

Sying-Jyan Wang, Po-Ching Hsu, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

Katherine Shu-Min Li, Sying-Jyan Wang, Jwu E. Chen, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power-Aware High-Level Synthesis With Clock Skew Management

Sying-Jyan Wang, Tung-Hua Yeh, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of sequential machines with reduced testing cost

Sying-Jyan Wang, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Test and diagnosis of faulty logic blocks in FPGAs

Sying-Jyan Wang, Tsi-Ming Tsai, 1999 .

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

Sying-Jyan Wang, Po-Chang Tsai, Sying-Jyan Wang, 2006, 2006 15th Asian Test Symposium.

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs

Sying-Jyan Wang, Nan-Cheng Lai, 2007, 16th Asian Test Symposium (ATS 2007).

Delay Test with Embedded Test Pattern Generator

Sying-Jyan Wang, Nan-Cheng Lai, 2013, J. Inf. Sci. Eng..

Low power parallel multiplier with column bypassing

Sying-Jyan Wang, Yen-Nan Lin, Mingchen Wen, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Systematic t-error correcting/all unidirectional error detecting codes with easy encoding/decoding

Niraj K. Jha, Sying-Jyan Wang, 1990 .

Design and synthesis of self-checking VLSI circuits and systems

Niraj K. Jha, Sying-Jyan Wang, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning

Katherine Shu-Min Li, Sying-Jyan Wang, Leon Chou, 2019, 2019 IEEE International Test Conference (ITC).

Low power BIST with smoother and scan-chain reorder

Sying-Jyan Wang, Nan-Cheng Lai, Yu-Hsuan Fu, 2004, 13th Asian Test Symposium.

Improving Output Compaction Efficiency with High Observability Scan Chains

Katherine Shu-Min Li, Sying-Jyan Wang, Che-Wei Kao, 2014, 2014 IEEE 23rd Asian Test Symposium.

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis

Sying-Jyan Wang, Bo-Chuan Cheng, Katherine Shu-Min Li, 2017, IEEE Design & Test.

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests

Sying-Jyan Wang, Nan-Cheng Lai, 2008, 2008 17th Asian Test Symposium.

Retiming-based logic synthesis for low-power

Sying-Jyan Wang, Yu-Lung Hsu, Yu-Lung Hsu, 2002, ISLPED '02.

Fast and accurate statistical static timing analysis

Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Huei Tzeng, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips

Tsung-Yi Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip

Katherine Shu-Min Li, Sying-Jyan Wang, Sying-Jyan Wang, 2017, ACM Trans. Design Autom. Electr. Syst..

TestDNA: Novel Wafer Defect Signature for Diagnosis and Pattern Recognition

Katherine Shu-Min Li, Sying-Jyan Wang, Peter Yi-Yu Liao, 2020, IEEE Transactions on Semiconductor Manufacturing.

Efficient built-in self-test algorithm for memory

Sying-Jyan Wang, Chen-Jung Wei, 2000, Proceedings of the Ninth Asian Test Symposium.

Low-cost testing of TSVs in 3D stacks with pre-bond testable dies

Katherine Shu-Min Li, Sying-Jyan Wang, Yu-Siao Chen, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

A reseeding technique for LFSR-based BIST applications

Sying-Jyan Wang, Nan-Cheng Li, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling

Yan-Ting Chen, Katherine Shu-Min Li, Sying-Jyan Wang, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Design and analysis of skewed-distribution scan chain partition for improved test data compression

Katherine Shu-Min Li, Sying-Jyan Wang, Shih-Cheng Chen, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Low peak power ATPG for n-detection test

Katherine Shu-Min Li, Sying-Jyan Wang, Kuo-Lin Fu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Digital Rights Management for Paper-Based Microfluidic Biochips

Tsung-Yi Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

Test and diagnosis of faulty logic blocks in FPGAs

Sying-Jyan Wang, Tsi-Ming Tsai, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint

Katherine Shu-Min Li, Sying-Jyan Wang, Shih-Cheng Chen, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test Data Compression with Partial LFSR-Reseeding

Sying-Jyan Wang, Yu-Hsuan Fu, 2005, 14th Asian Test Symposium (ATS'05).

Side-Channel Attack on Flipped Scan Chains

Katherine Shu-Min Li, Sying-Jyan Wang, Ting-Jui Choi, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Katherine Shu-Min Li, Sying-Jyan Wang, Chin-Hung Lien, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A 1.8 V to 3.3 V level-converting flip-flop design for multiple power supply systems

Chua-Chin Wang, Katherine Shu-Min Li, Sying-Jyan Wang, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator

Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2013, 2013 22nd Asian Test Symposium.

Adaptive system-level diagnosis and its application

Sying-Jyan Wang, 1997, Proceedings Pacific Rim International Symposium on Fault-Tolerant Systems.

Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips

Shiyan Hu, Hung-Ming Chen, Tsung-Yi Ho, 2019, Microelectron. J..

Algorithm-based fault tolerance for FFT networks

Niraj K. Jha, Sying-Jyan Wang, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Distributed Diagnosis in Multistage Interconnection Networks

Sying-Jyan Wang, 2001, J. Parallel Distributed Comput..

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

Sying-Jyan Wang, Po-Chang Tsai, 2006 .

Distributed Routing in a Fault-Tolerant Multistage Interconnection Network

Sying-Jyan Wang, 1997, Inf. Process. Lett..

Design-for-testability for paper-based digital microfluidic biochips

Tsung-Yi Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2017, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Testing and diagnosis of interconnect structures in FPGAs

Sying-Jyan Wang, Chao-Neng Huang, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Algorithm-Based Fault Tolerance for FFT Networks

Niraj K. Jha, Sying-Jyan Wang, 1994, IEEE Trans. Computers.

FSM-based programmable memory BIST with macro command

Sying-Jyan Wang, Po-Chang Tsai, Feng-Ming Chang, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

Synthesis of 3D clock tree with pre-bond testability

Katherine Shu-Min Li, Sying-Jyan Wang, Cheng-Hao Lin, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process

Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Innovative Practice on Wafer Test Innovations

Katherine Shu-Min Li, Sying-Jyan Wang, Ken Chau-Cheung Cheng, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning

Katherine Shu-Min Li, Sying-Jyan Wang, Leon Chou, 2020, 2020 IEEE International Test Conference (ITC).