Ruei-Ting Gu

Optimized Pre-bond Test Methodology for Silicon Interposer Testing

Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, 2014, 2014 IEEE 23rd Asian Test Symposium.

A Unified Interconnects Testing Scheme for 3D Integrated Circuits

Liang-Bi Chen, Katherine Shu-Min Li, Ruei-Ting Gu, 2011, 2011 Asian Test Symposium.

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package

Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang, 2013, 2013 22nd Asian Test Symposium.

A layout-aware test methodology for silicon interposer in 3D System-in-a-Package

Liang-Bi Chen, Yingchieh Ho, Sying-Jyan Wang, 2013, 2013 International Symposium on Next-Generation Electronics.

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics

Ing-Jer Huang, Liang-Bi Chen, Chien-Chou Wang, 2009, 2009 Asia and South Pacific Design Automation Conference.

Fault-tolerant mesh for 3D network on chip

Katherine Shu-Min Li, Ruei-Ting Gu, Bo-Chuan Cheng, 2011, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics

Ing-Jer Huang, Ming-Chao Chiang, Shen-Fu Hsiao, 2007, 2007 IEEE International Symposium on Consumer Electronics.

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics

Ing-Jer Huang, Chien-Chou Wang, Jin-Hua Hong, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A fast custom network topology generation with floorplanning for NoC-based systems

Liang-Bi Chen, Katherine Shu-Min Li, Ruei-Ting Gu, 2011, 2011 IEEE International Conference on IC Design & Technology.