Fernando Martinez-Vallina

Unlocking FPGAs Using High Level Synthesis Compiler Technologies

Henry Styles, Fernando Martinez-Vallina, 2015, FPGA.

Performance optimization for a SHA-1 cryptographic workload expressed in OpenCL for FPGA execution

Spenser Gilliland, Fernando Martinez-Vallina, 2015, IWOCL.

Analysis of library functions for FPGA compute accelerators

Jafar Saniie, Spenser Gilliland, Fernando Martinez-Vallina, 2017, 2017 IEEE International Conference on Electro Information Technology (EIT).

OpenCL library of stream memory components targeting FPGAs

Ralph Wittig, Paul Schumacher, Henry Styles, 2015, 2015 International Conference on Field Programmable Technology (FPT).

Image and video processing platform for field programmable gate arrays using a high-level synthesis

Christophe Desmouliers, Erdal Oruklu, Jafar Saniie, 2012, IET Comput. Digit. Tech..

CReconfigurable finite field instruction set architecture

Jafar Saniie, Fernando Martinez-Vallina, Nathan Jachimiec, 2007, FPGA '07.

Building zynq® accelerators with Vivado® high level synthesis

Stephen Neuendorffer, Fernando Martinez-Vallina, S. Neuendorffer, 2013, FPGA '13.

Implementation of elementary functions for FPGA compute accelerators

Jafar Saniie, Spenser Gilliland, Fernando Martinez-Vallina, 2016, 2016 IEEE International Conference on Electro Information Technology (EIT).

Developing optimized libraries for scalable OpenCL acceleration on FPGAs

Devadas Varma, Fernando Martinez-Vallina, Vinay Singh, 2015, International Workshop on OpenCL.