Y. Wada

AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design

I. Ishida, Y. Wada, M. Hidaka, 1988 .

A 570ps, 13mW Josephson 1kb Ram

Y. Wada, S. Nagasawa, I. Ishida, 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

A fabrication process for a 580 ps 4 kbit Josephson non-destructive read-out RAM

Shuichi Nagasawa, Shuichi Tahara, Mutsuo Hidaka, 1991 .

A 4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6.7 mW

Shuichi Nagasawa, Shuichi Tahara, Mutsuo Hidaka, 1991 .

570-ps 13-mW Josephson 1-kbit NDRO RAM

Shuichi Nagasawa, Shuichi Tahara, Mutsuo Hidaka, 1989 .

Nb multilayer planarization technology for a subnanosecond Josephson 1K-bit RAM

Shuichi Nagasawa, Shuichi Tahara, Mutsuo Hidaka, 1989 .

An RCJL decoder for a Josephson memory

I. Ishida, Y. Wada, M. Hidaka, 1983, IEEE Electron Device Letters.

Josephson memory technology

Y. Wada, Y. Wada, 1989, Proc. IEEE.