Rahul M. Rao

发表

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies

Ching-Te Chuang, Saibal Mukhopadhyay, Rahul M. Rao, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics

Anindya Sundar Dhar, Rahul M. Rao, Sumantra Sarkar, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parametric yield analysis and constrained-based supply voltage optimization

Kevin J. Nowka, Dennis Sylvester, Richard B. Brown, 2005, Sixth international symposium on quality electronic design (isqed'05).

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator

Masanori Hashimoto, Sani R. Nassif, Rahul M. Rao, 2013, 2013 18th IEEE European Test Symposium (ETS).

A precise Negative Bias Temperature Instability sensor using slew-rate monitor circuitry

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2009, 2009 IEEE International Symposium on Circuits and Systems.

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Impact of Device Aging on Early Mode Failures in Pulsed Latches

Rahul M. Rao, Ankur Shukla, James D. Warnock, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Analysis and optimization of enhanced MTCMOS scheme

Richard B. Brown, Rahul M. Rao, Jeffrey L. Burns, 2004, 17th International Conference on VLSI Design. Proceedings..

Power-aware global signaling strategies

Himanshu Kaul, Sani R. Nassif, Dennis Sylvester, 2005, 2005 IEEE International Symposium on Circuits and Systems.

IBM POWER9 circuit design and energy optimization for 14-nm technology

Rahul M. Rao, Alper Buyuktosunoglu, Howard Smith, 2018, IBM J. Res. Dev..

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

Frank Liu, Richard B. Brown, Rahul M. Rao, 2003, ICCAD.

IBM POWER8 circuit design and energy optimization

Matthew M. Ziegler, Victor V. Zyuban, Rahul M. Rao, 2015, IBM J. Res. Dev..

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

Victor V. Zyuban, Arun Joseph, Nagu R. Dhanwada, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength

Kevin J. Nowka, Dennis Sylvester, Rahul M. Rao, 2005, Proceedings 2005 IEEE International SOC Conference.

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficient techniques for gate leakage estimation

Richard B. Brown, Rahul M. Rao, Anirudh Devgan, 2003, ISLPED '03.

Leakage and leakage sensitivity computation for combinational circuits

Ying Liu, Sani R. Nassif, Emrah Acar, 2003, ISLPED '03.

Approaches to run-time and standby mode leakage reduction in global buses

Kevin J. Nowka, Sani R. Nassif, Dennis Sylvester, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Virtual logic netlist: Enabling efficient RTL analysis

Arun Joseph, Rahul M. Rao, Diwesh Pandey, 2015, Sixteenth International Symposium on Quality Electronic Design.

A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits

Rahul M. Rao, Nitin Chandrachoodan, Shivani Bathla, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization

Kevin J. Nowka, Dennis Sylvester, Richard B. Brown, 2005, Sixth international symposium on quality electronic design (isqed'05).

A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement

Keith A. Jenkins, Rahul M. Rao, Jae-Joon Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Ching-Te Chuang, Saibal Mukhopadhyay, Rahul M. Rao, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Ching-Te Chuang, Rahul M. Rao, Jae-Joon Kim, 2009, Microelectron. Reliab..

A High Performance Gated Voltage Level Translator with Integrated Multiplexer

Rahul M. Rao, S. DharshakB., 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise

Dennis Sylvester, Richard B. Brown, Rahul M. Rao, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Power optimization methodology for the IBM POWER7 microprocessor

Rahul M. Rao, Sam Gat-Shang Chu, M. D. Brown, 2011 .

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation

Richard B. Brown, Rahul M. Rao, Amlan Ghosh, 2009, ISLPED.

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4

Rahul M. Rao, Juergen Pille, Michael S. Floyd, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Variations: Sources and Characterization

Rahul M. Rao, Aditya Bansal, 2011, Low-Power Variation-Tolerant Design in Nanometer Silicon.

Frequency estimation by linear prediction

Frank K. Soong, Donald W. Tufts, Rahul M. Rao, 1978, ICASSP.

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies

Dennis Sylvester, Richard B. Brown, Rahul M. Rao, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Rahul M. Rao, Jae-Joon Kim, Keunwoo Kim, 2010, IEEE Custom Integrated Circuits Conference 2010.

Approaches to Run-Time and Standby Mode Leakage Reduction in Global Buses

Sani R. Nassif, Dennis Sylvester, Richard B. Brown, 2004 .

FVCAG: A framework for formal verification driven power modeling and verification

Arun Joseph, Rahul M. Rao, Pradeep Kumar Nalla, 2016, ISLPED.

Energy Efficiency Boost in the AI-Infused POWER10 Processor

Pradip Bose, José E. Moreira, Balaram Sinharoy, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

Reliability monitoring ring oscillator structures for isolated/combined NBTI and PBTI measurement in high-k metal gate technologies

Barry P. Linder, Ching-Te Chuang, Chris H. Kim, 2011, 2011 International Reliability Physics Symposium.

ANALYSIS AND MITIGATION OF CMOS GATE LEAKAGE

Rahul M. Rao, Jeffrey L. Burns, Kevin Nowka, 2004 .

On-chip Process Variation Detection and Compensation for Parametric Yield Enhancement in sub-100 nm CMOS technology

Rahul M. Rao, Amlan Ghosh, Richard B. Brown, 2007 .

PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability

Barry P. Linder, Rahul M. Rao, Amlan Ghosh, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

On-chip Negative Bias Temperature Instability Sensor using Slew Rate Monitoring Circuitry

Ching-Te Chuang, Rahul M. Rao, Amlan Ghosh, 2008 .