Jae-Joon Kim

发表

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies

Ching-Te Chuang, Saibal Mukhopadhyay, Rahul M. Rao, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Yandong Luo, Xiaoyu Sun, Shimeng Yu, 2019, IEEE Micro.

Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors

Jae-Joon Kim, Jinseok Kim, Jongeun Koo, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

High-PerformanceDeviceOptimizationandDual-VT Technology Options forDoubleGate FET

Ching-Te Chuang, Jae-Joon Kim, Aditya Bansal, 2007 .

Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs

Sunggu Lee, Dongyoung Kim, Sungjoo Yoo, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines

Eunhyeok Park, Dongyoung Kim, Sungjoo Yoo, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Maximizing system performance by balancing computation loads in LSTM accelerators

Jae-Joon Kim, Jaeha Kung, Wooseok Yi, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Novel In-DRAM Accelerator Architecture for Binary Neural Network

Sungjoo Yoo, Jae-Joon Kim, Haerang Choi, 2020, 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics

Jinseok Kim, Jae-Joon Kim, Taesu Kim, 2017, ACM J. Emerg. Technol. Comput. Syst..

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation

Jae-Joon Kim, Youngsoo Shin, Insup Shin, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors

Kaushik Roy, Dongsoo Lee, Jae-Joon Kim, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2006, 2006 European Solid-State Device Research Conference.

Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

Sungho Kim, Jinseok Kim, Jae-Joon Kim, 2018, ISLPED.

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

Kaushik Roy, Chris H. Kim, Saibal Mukhopadhyay, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

VLSI-SoC: Design for Reliability, Security, and Low Power

Chi-Ying Tsui, Kiyoung Choi, Jae-Joon Kim, 2015, IFIP Advances in Information and Communication Technology.

Robust Level Converter Design for Sub-threshold Logic

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Bias Temperature Instability model for digital circuits - predicting instantaneous FET response

Jae-Joon Kim, Kai Zhao, Aditya Bansal, 2011, 2011 International Reliability Physics Symposium.

Asymmetrical SRAM Cells with Enhanced Read and Write Margins

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array

Jinseok Kim, Jae-Joon Kim, Taesu Kim, 2019, 2019 Symposium on VLSI Circuits.

Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware

Jinseok Kim, Jae-Joon Kim, Taesu Kim, 2018, Front. Neurosci..

Time-step interleaved weight reuse for LSTM neural network computing

Jae-Joon Kim, Taesu Kim, Yulhwa Kim, 2020, ISLPED.

Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array

Jae-Joon Kim, Yulhwa Kim, Wooseok Yi, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design

Jae-Joon Kim, Hai Li, Xiuyuan Bi, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Forward Body-Biased Low-Leakage SRAM Cache: Device and Arch i tect u re Cons iderat ions

Kaushik Roy, Saibal Mukhopadhyay, Jae-Joon Kim, 2003 .

Double Viterbi: Weight Encoding for High Compression Ratio and Fast On-Chip Reconstruction for Deep Neural Network

Dongsoo Lee, Jae-Joon Kim, Taesu Kim, 2018, ICLR.

Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2005, Sixth international symposium on quality electronic design (isqed'05).

2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning

Xiaoyu Sun, Shimeng Yu, Jae-Joon Kim, 2020, IEEE Solid-State Circuits Letters.

A Study of Commercial Rental Properties within a Large Complex Facility by Measuring the Spatial Structure

Jae-Joon Kim, Byung-Ju Ahn, Jae-Hong Hwang, 2010 .

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2007, Microelectron. J..

High-performance SRAM in nanoscale CMOS: Design challenges and techniques

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors

Jae-Joon Kim, Minah Lee, Eunhwan Kim, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A review of on-chip timing error detection/correction methods for logic pipeline

Jae-Joon Kim, 2015, 2015 International SoC Design Conference (ISOCC).

A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS

Jae-Joon Kim, Taesu Kim, Yulhwa Kim, 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).

GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Learning

Jae-Joon Kim, Wooseok Yi, Junki Park, 2017, 2017 International Symposium on Rapid System Prototyping (RSP).

Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead

Jae-Joon Kim, Yulhwa Kim, Sungju Ryu, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning

Jae-Joon Kim, Taesu Kim, Daehyun Ahn, 2020, FPGA.

Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware

Jae-Joon Kim, Taesu Kim, Jinseok Kim, 2017, IEEE Electron Device Letters.

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling

Jae-Joon Kim, Youngsoo Shin, Insup Shin, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Separating NBTI and PBTI effects on the degradation of Ring Oscillator frequency

Barry P. Linder, Jae-Joon Kim, Aditya Bansal, 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.

A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement

Keith A. Jenkins, Rahul M. Rao, Jae-Joon Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Ching-Te Chuang, Saibal Mukhopadhyay, Rahul M. Rao, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Ching-Te Chuang, Rahul M. Rao, Jae-Joon Kim, 2009, Microelectron. Reliab..

Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio

Dongsoo Lee, Jae-Joon Kim, Taesu Kim, 2018, ICLR.

Column-selection-enabled 8T SRAM array with

Dongsoo Lee, Jae-Joon Kim, Sang Phill Park, 2011, ISLPED 2011.

Low design overhead timing error correction scheme for elastic clock methodology

Jae-Joon Kim, Jongeun Koo, Sungju Ryu, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET

C.H. Kim, Jae-Joon Kim, H. Ananthan, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

Jae-Joon Kim, Hyungjun Kim, Yulhwa Kim, 2018, ISLPED.

Usage-based degradation of SRAM arrays due to bias temperature instability

Jae-Joon Kim, R. Rao, A. Bansal, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

RobustLevel Converter Design forSub-threshold Logic

Kaushik Roy, Jae-Joon Kim, 2006 .

Self-Repairing SRAM Using On-Chip Detection and Compensation

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators pdf

Jae-Joon Kim, Yulhwa Kim, Hyungjun Kim, 2018, ArXiv.

Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

Jae-Joon Kim, Sungju Ryu, Naebeom Park, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors

Ching-Te Chuang, Jae-Joon Kim, Shih-Hsien Lo, 2009, IEEE Electron Device Letters.

Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2008, IEEE Transactions on Electron Devices.

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2009, IEEE Journal of Solid-State Circuits.

In-memory batch-normalization for resistive memory based binary neural network hardware

Jae-Joon Kim, Yulhwa Kim, Hyungjun Kim, 2019, ASP-DAC.

Implementation of a scout image-based medical image information system

Jae-Joon Kim, 2007 .

A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry

Jae-Joon Kim, K.A. Jenkins, R. Rao, 2009, IEEE Journal of Solid-State Circuits.

Back-gate controlled READ SRAM with improved stability

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2005, 2005 IEEE International SOI Conference Proceedings.

A forward body-biased low-leakage SRAM cache: device and architecture considerations

Kaushik Roy, Chris H. Kim, Saibal Mukhopadhyay, 2003, ISLPED '03.

A pipeline architecture with 1-cycle timing error correction for low voltage operations

Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement

Rahul M. Rao, Jae-Joon Kim, Keunwoo Kim, 2010, IEEE Custom Integrated Circuits Conference 2010.

High-Performance Device Optimization and Dual-VT Technology Options for DoubleGate FET

Ching-Te Chuang, Jae-Joon Kim, Keunwoo Kim, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.