Nakahara Hiroki

发表

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks

Kuramochi Ryosuke, Sada Youki, Shimoda Masayuki, 2020 .

Accurate Pedestrian Detection in Thermal Images for FPGA

Kuramochi Ryosuke, Sada Youki, Shimoda Masayuki, 2019 .

An FPGA Implementation of Monocular Depth Estimation

Sada Youki, Shimoda Masayuki, Sato Shimpei, 2020 .

Model Compression for ECG Signals Outlier Detection Hardware trained by Sparse Robust Deep Autoencoder

Sato Shimpei, Nakahara Hiroki, Soga Naoto, 2019 .

Dynamic Reconfigurable PLA on FPGA and DSL-based Design Methodology

Nakahara Hiroki, Miyoshi Takefumi, Funada Satoshi, 2015 .

A Packet Classifier using Parallel EVMDD(k) Machine

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2013 .

A method to evaluate logic function by using decision diagram with memory packing.

Nakahara Hiroki, Tanaka Hiroyuki, Sasao Tsutomu, 2007 .

An Architecture for IPv6 Lookup Using Parallel Index Generation Units

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2013 .

A Winning Board Detector Using an Index Generation Unit

Nakahara Hiroki, Shiihara Kousiro, Idokawa Yuki, 2012 .

A Packet Classifier Using a Parallel Branching Program Machine

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2010 .

GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA

Shimoda Masayuki, Sato Shimpei, Nakahara Hiroki, 2017 .

A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization

Sato Shimpei, Nakahara Hiroki, Fujii Tomoya, 2017 .

An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure

Sada Youki, Shimoda Masayuki, Sato Shimpei, 2019 .

A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS)

Sato Shimpei, Nakahara Hiroki, Cheng Haoxuan, 2018 .

A Logic Simulation using an LUT Cascade Emulator

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2005 .

A Fault Tolerant LUT Cascade Emulator

Nakahara Hiroki, Sasao Tsutomu, 2006 .

Spatial-Separable Convolution: Low memory CNN for FPGA

Shimoda Masayuki, Nakahara Hiroki, Jinguji Akira, 2019 .

All Binarized Conventional Neural Network and its Implementation on an FPGA -- FPT2017 Design Competition Report

Shimoda Masayuki, Sato Shimpei, Nakahara Hiroki, 2018 .

An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL

Sato Shimpei, Nakahara Hiroki, Yonekawa Haruyoshi, 2018 .

Accelerated Ternarized Deep Neural Network by sparse matrix calculation

Sato Shimpei, Nakahara Hiroki, Motomura Masato, 2017 .

A Method of Design and Update for an Address Generator Using a Hybrid Method

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2008 .

A Comparison of Two Approximate String Matching Algorithms Implemented on an FPGA

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2010 .

An Implementation of an Object Detector on an FPGA

Shimoda Masayuki, Sato Shimpei, Nakahara Hiroki, 2018 .

A Regular Expression Matching Circuit Based on an NFA with Multi-Character Consuming

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2010 .

Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement

Nakahara Hiroki, Motomura Masato, Yonekawa Haruyoshi, 2017 .

An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL

Sada Youki, Shimoda Masayuki, Sato Shimpei, 2018 .

FPGA Implementation of Fully Convolutional Network for Semantic Segmentation

Sada Youki, Shimoda Masayuki, Nakahara Hiroki, 2019 .

A Virus Scanning Engine Using a Parallel Sieve Method and the MPU

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2009 .

Efficient Object Detection with Event-Driven camera and its implementation on an FPGA

Shimoda Masayuki, Sato Shimpei, Nakahara Hiroki, 2018 .

FPGA implementation of ISA-based sparse CNN using Wide-SIMD

Sato Shimpei, Nakahara Hiroki, Jinguji Akira, 2019 .

A Memory Based Realization of the Binarized Deep Convolutional Neural Network

Nakahara Hiroki, Motomura Masato, Iwamoto Hisashi, 2016 .

On a Prefetching Heterogeneous MDD Machine

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2010 .

A CAM Emulator Using Look-Up Table Cascades

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2007 .

An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2013 .

A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique

Nakahara Hiroki, Jinguji Akira, Sato Simpei, 2018 .

On a Power-Delay Product for a Heterogeneous MDD for ECFN Machine

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2011 .

An Acceleration of a Random Forest Classification using Altera SDK for OpenCL

Nakahara Hiroki, Maruyama Naoya, Fujii Tomoya, 2016 .

Hardware implementation of ECG signals outlier detector trained by Sparse Robust Deep Autoencoder

Sato Shimpei, Nakahara Hiroki, Soga Naoto, 2018 .

A Low-Power Intelligent Camera using an FPGA toward Internet of Things Agriculture

Nakahara Hiroki, Morimoto Tetsuo, Kurose Takahisa, 2016 .

A Design Method Using Discrete Particle Swarm Optimization for a Deep Neural Network Based on Nested RNS

Nakahara Hiroki, Sasao Tsutomu, Ogawa Tatsuya, 2015 .

A Dynamic Reconfigurable Mixed Analog-Digital Filter -- Applied to an Acoustic Diagnostic

Nakahara Hiroki, Sasao Tsutomu, Yoshida Hideki, 2014 .

Emulation of Sequential Circuits by a Parallel Branching Program Machine

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2009 .

A Virus Scanning Engine Using an MPU and an IGU Based on ROW Shift Decomposition

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2012 .

A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL

Nakahara Hiroki, Maruyama Naoya, Fujii Tomoya, 2016 .

On a Decomposed MTMDDs for CF Machine

Nakahara Hiroki, Sasao Tsutomu, Matsuura Munehiro, 2012 .

A High-Speed FFT for a Solar Radio Burst Obvervation on a Radio Telescope

Nakahara Hiroki, Chishiki Youhei, Iwai Kazumasa, 2013 .

A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division

Nakahara Hiroki, Iwamoto Hisashi, Sasao Tsutomu, 2016 .

A CNN with a Noise Addition for Efficient Implementation on an FPGA

Nakahara Hiroki, Munakata Atsuki, Satou Shimpei, 2019 .

An Implementation of AND-EXOR Programmable Logic Arrays Using FPGA primitives

Nakahara Hiroki, Sasao Tsutomu, Shinohara Takahiro, 2015 .

A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization

Nakahara Hiroki, Motomura Masato, Fujii Tomoya, 2017 .

Consideration of All Binarized Convolutional Neural Network

Shimoda Masayuki, Sato Shimpei, Nakahara Hiroki, 2017 .

A Deep Convolutional Neural Network Based on Nested Residue Number System

Nakahara Hiroki, Sasao Tsutomu, 2015 .