Paritosh Bhoraskar

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

Qicheng Yu, Ning Zhu, Gerry Taylor, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

Ho-Young Lee, Janet Brunsilius, Carroll Speir, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration

Janet Brunsilius, Carroll Speir, Hüseyin Dinc, 2014, IEEE Journal of Solid-State Circuits.

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

Ahmed M. A. Ali, Huseyin Dinc, Paritosh Bhoraskar, 2020, IEEE Journal of Solid-State Circuits.