Balraj Singh

Field projects reports of MAE.

Balraj Singh, 2009 .

Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors

Deepti Gola, Satyabrata Jit, Balraj Singh, 2017 .

2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect

Deepti Gola, Satyabrata Jit, Balraj Singh, 2017, IEEE Transactions on Electron Devices.

Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects

Jawar Singh, Deepti Gola, Satyabrata Jit, 2019, IEEE Transactions on Electron Devices.

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

Deepti Gola, Satyabrata Jit, Balraj Singh, 2016 .

Temperature Sensitivity Analysis of Double Gate Junctionless Field Effect Transistor with Vertical Gaussian Doping Profile

Deepti Gola, Satyabrata Jit, Balraj Singh, 2016, 2016 International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE).

2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs

Satyabrata Jit, Balraj Singh, Kunal Singh, 2016, IEEE Transactions on Electron Devices.

A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

Deepti Gola, Pramod Kumar Tiwari, Balraj Singh, 2017, IEEE Transactions on Electron Devices.

Subthreshold Modeling of Tri-Gate Junctionless Transistors With Variable Channel Edges and Substrate Bias Effects

Deepti Gola, Pramod Kumar Tiwari, Balraj Singh, 2018, IEEE Transactions on Electron Devices.

A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High- $k$ Stacked Gate-Oxide Structure

Satyabrata Jit, Balraj Singh, Kunal Singh, 2016, IEEE Transactions on Electron Devices.

Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

Satyabrata Jit, Sarvesh Dubey, Balraj Singh, 2016, Journal of Electronic Materials.